MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 748

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 20 S12X Debug (S12XDBGV3) Module
750
DBGBRK
XGSBPE
COMRV
Field
TRIG
ARM
BDM
3–2
1–0
7
6
5
4
Arm Bit — The ARM bit controls whether the S12XDBG module is armed. This bit can be set and cleared by
user software and is automatically cleared on completion of a tracing session, or if a breakpoint is generated with
tracing not enabled. On setting this bit the state sequencer enters State1. When ARM is set, the only bits in the
S12XDBG module registers that can be written are ARM and TRIG.
0 Debugger disarmed
1 Debugger armed
Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of
comparator or external tag signal status. When tracing is complete a forced breakpoint may be generated
depending upon DBGBRK and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no
effect. If both TSOURCE bits are clear no tracing is carried out. If tracing has already commenced using BEGIN-
or MID trigger alignment, it continues until the end of the tracing session as defined by the TALIGN bit settings,
thus TRIG has no affect. In secure mode tracing is disabled and writing to this bit has no effect.
0 Do not trigger until the state sequencer enters the Final State.
1 Enter Final State immediately and issue forced breakpoint request when trace buffer is full.
XGATE S/W Breakpoint Enable — The XGSBPE bit controls whether an XGATE S/W breakpoint request is
passed to the S12XCPU. The XGATE S/W breakpoint request is handled by the S12XDBG module, which can
request an S12XCPU breakpoint depending on the state of this bit.
0 XGATE S/W breakpoint request is disabled
1 XGATE S/W breakpoint request is enabled
Background Debug Mode Enable — This bit determines if a S12X breakpoint causes the system to enter
Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). It has no affect on S12XDBG functionality.
If this bit is set but the BDM is not enabled by the ENBDM bit in the BDM module, then breakpoints default to SWI.
0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.
1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI
S12XDBG Breakpoint Enable Bits — The DBGBRK bits control whether the debugger will request a breakpoint
to either S12XCPU or XGATE or both upon reaching the state sequencer Final State. If tracing is enabled, the
breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is
generated immediately. Please refer to
independent of the DBGBRK bits. XGATE software breakpoints force a breakpoint to the S12XCPU independent
of the DBGBRK bit field configuration. See
Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the
8-byte window of the S12XDBG module address map, located between 0x0028 to 0x002F. Furthermore these
bits determine which register is visible at the address 0x0027. See
DBGBRK
COMRV
00
01
00
01
10
11
No breakpoint generated
XGATE breakpoint generated
S12XCPU breakpoint generated
Breakpoints generated for S12XCPU and XGATE
Visible Comparator
Table 20-3. DBGC1 Field Descriptions
Comparator A
Comparator B
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 20-4. DBGBRK Encoding
Table 20-5. COMRV Encoding
Section 20.4.7
Resource Halted by Breakpoint
Table
20-4.
Description
for further details. XGATE software breakpoints are
Visible Register at 0x0027
Table
DBGSCR1
DBGSCR2
20-5.
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