MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 755

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3.2.6
Read: Anytime
Write: Never
Freescale Semiconductor
Address: 0x0026
CNT[6:0]
Reset
Field
POR
6–0
W
R
1
This applies to Normal/Loop1 Modes when tracing from either S12XCPU or XGATE only.
TBF (DBGSR)
Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the Trace Buffer.
Table 20-18
When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in
end-trigger or mid-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The
DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus
should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of
valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when
reading from the trace buffer.
Debug Count Register (DBGCNT)
0
0
0
7
0
0
0
0
1
1
= Unimplemented or Reserved
shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer.
—
0
6
CNT[6:0]
0000000
0000001
0000010
0000100
0000110
1111100
1111110
0000000
0000010
1111110
Figure 20-8. Debug Count Register (DBGCNT)
..
..
..
Table 20-17. DBGCNT Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
Table 20-18. CNT Decoding Table
—
0
5
ARM bit will be cleared and the tracing session ends.
oldest data has been overwritten by most recent data
64 lines valid; if using Begin trigger alignment,
—
0
4
Description
32 bits of one line valid
CNT
—
64 lines valid,
No data valid
62 lines valid
63 lines valid
0
3
Description
2 lines valid
3 lines valid
1 line valid
..
Chapter 20 S12X Debug (S12XDBGV3) Module
—
0
2
1
—
0
1
—
0
0
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