MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 795

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.4.2.2.2
Freescale Semiconductor
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (write)
R/W
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (write)
R/W
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (write)
R/W
Write Access Timing
...
...
...
...
...
...
addr 0
high
?
0
Table 21-14. Write Access (n–1 Cycles)
Table 21-13. Write Access (2 Cycles)
Table 21-12. Write Access (1 Cycle)
...
...
...
...
...
...
...
...
...
...
...
...
1
MC9S12XDP512 Data Sheet, Rev. 2.21
iqstat-1
acc 0
low
addr 0
addr 0
?
0
high
high
Access #0
?
0
?
0
1
1
addr 0
iqstat -1
high
iqstat-1
acc 0
acc 0
0
low
low
Access #0
Access #0
?
0
?
0
data 0
2
iqstat 0
000
low
addr 0
addr 1
x
0
high
high
Access #1
1
0
data 0
data 0
2
2
addr 0
iqstat 0
iqstat 0
high
acc 1
0
000
low
low
Chapter 21 External Bus Interface (S12XEBIV2)
x
1
x
0
data 1
3
0000
000
low
addr 2
addr 1
x
0
high
high
Access #2
Access #1
1
1
...
...
...
...
...
...
3
3
iqstat 1
data 2
acc 2
acc 1
0000
low
low
addr 1
x
1
x
x
1
high
Access #1
1
...
...
...
...
...
...
...
...
...
...
...
...
...
...
n
acc 1
0000
low
x
x
1
797
...
...
...
...
...
...
...