MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 798

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 21 External Bus Interface (S12XEBIV2)
21.4.5.2
In emulation modes and special test mode, the external signals LSTRB, R/W, and ADDR0 indicate the
access type (read/write), data size and alignment of an external bus access. Misaligned accesses to the
internal RAM and misaligned XGATE PRR accesses in emulation modes are the only type of access that
are able to produce LSTRB = ADDR0 = 1. This is summarized in
800
Word write of data on DATA[15:0] at an even and even+1 address
Byte write of data on DATA[7:0] at an odd address
Byte write of data on DATA[15:8] at an even address
Word read of data on DATA[15:0] at an even and even+1 address
Byte read of data on DATA[7:0] at an odd address
Byte read of data on DATA[15:8] at an even address
Indicates No Access
Unimplemented
Word write of data on DATA[15:0] at an even and even+1
address
Byte write of data on DATA[7:0] at an odd address
Byte write of data on DATA[15:8] at an even address
Word write at an odd and odd+1 internal RAM address
(misaligned — only in emulation modes)
Word read of data on DATA[15:0] at an even and even+1
address
Byte read of data on DATA[7:0] at an odd address
Byte read of data on DATA[15:8] at an even address
Word read at an odd and odd+1 internal RAM address
(misaligned - only in emulation modes)
Emulation Modes and Special Test Mode
Table 21-18. Access in Emulation Modes and Special Test Mode
Access
Access
Table 21-17. Access in Normal Expanded Mode
MC9S12XDP512 Data Sheet, Rev. 2.21
R/W LSTRB ADDR0
0
0
0
0
1
1
1
1
RE WE UDS LDS
1
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
1
1
1
1
Table
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
1
0
Out
Out
Out data(odd+1) Out
0
0
1
0
0
1
1
0
1
I/O
21-18.
In
In
In
In
In
DATA[15:8]
Out data(even) Out data(odd)
Out data(even)
I/O data(addr) I/O data(addr)
In
In
In
In
In
In
In
data(odd+1)
data(addr)
data(even)
data(even)
data(even)
data(odd)
DATA[15:8]
data(even)
data(even)
x
x
Freescale Semiconductor
x
x
x
x
x
Out
Out
I/O
In
In
In
In
In
Out data(odd)
In
In
In
In
In
In
In
DATA[7:0]
DATA[7:0]
data(even+1)
data(addr)
data(odd)
data(odd)
data(odd)
data(odd)
data(odd)
data(odd)
data(odd)
x
x
x
x
x
x
x