MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 829

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.3.2.7
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
22.3.2.8
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Freescale Semiconductor
DDRC[7:0]
DDRD[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
DDRC7
DDRD7
Data Direction Port C — This register controls the data direction for port C. When Port C is operating as a general
purpose I/O port, DDRC determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
Data Direction Port D — This register controls the data direction for port D. When Port D is operating as a general
purpose I/O port, DDRD determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
Port C Data Direction Register (DDRC)
Port D Data Direction Register (DDRD)
0
0
7
7
on PORTC after changing the DDRC register.
on PORTD after changing the DDRD register.
DDRC6
DDRD6
0
0
6
6
Figure 22-10. Port D Data Direction Register (DDRD)
Figure 22-9. Port C Data Direction Register (DDRC)
Table 22-10. DDRC Field Descriptions
Table 22-11. DDRD Field Descriptions
DDRC5
DDRD5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
5
DDRC4
DDRD4
0
0
4
4
Description
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
DDRC3
DDRD3
0
0
3
3
DDRC2
DDRD2
0
0
2
2
DDRC1
DDRD1
0
0
1
1
DDRC0
DDRD0
0
0
0
0
831