MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 933

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDRS[7:0]
Reset
Reset
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This also can be used to
detect overload or short circuit conditions on output pins.
23.0.5.25 Port S Data Direction Register (DDRS)
Read: Anytime.
Write: Anytime.
This register configures each port S pin as either input or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins.
The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if
the SCI receive channel is enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is
disabled.
Field
23.0.5.26 Port S Reduced Drive Register (RDRS)
Read: Anytime.
Write: Anytime.
7–0
W
W
R
R
DDRS7
RDRS7
Data Direction Port S
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
7
0
7
0
on PTS or PTIS registers, when changing the DDRS register.
DDRS6
RDRS6
0
0
6
6
Figure 23-28. Port S Reduced Drive Register (RDRS)
Figure 23-27. Port S Data Direction Register (DDRS)
Table 23-27. DDRS Field Descriptions
DDRS5
RDRS5
5
0
5
0
DDRS4
RDRS4
0
0
4
4
Description
DDRS3
RDRS3
3
0
3
0
DDRS2
RDRS2
0
0
2
2
DDRS1
RDRS1
1
0
1
0
DDRS0
RDRS0
0
0
0
0