MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 983

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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24.0.5
Table 24-3
level (IO), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the
ports.
The configuration bit PS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
Address
0x026C
0x026D
0x027C
0x027D
0x026A
0x026B
0x026E
0x026F
0x027A
0x027B
0x027E
0x027F
0x0267
0x0268
0x0269
0x0270
0x0277
0x0278
0x0279
1. Write access not applicable for one or more register bits. Refer to
summarizes the effect on the various configuration bits, data direction (DDR), output
Register Descriptions
ter
:
Descriptions”.
Port H Interrupt Flag Register (PIFH)
Port J Data Register (PTJ)
Port J Input Register (PTIJ)
Port J Data Direction Register (DDRJ)
Port J Reduced Drive Register (RDRJ)
Port J Pull Device Enable Register (PERJ)
Port J Polarity Select Register (PPSJ)
Port J Interrupt Enable Register (PIEJ)
Port J Interrupt Flag Register (PIFJ)
PIM Reserved
Port AD1 Data Register 0 (PT0AD1)
Port AD1 Data Register 1 (PT1AD1)
Port AD1 Data Direction Register 0 (DDR0AD1)
Port AD1 Data Direction Register 1 (DDR1AD1)
Port AD1 Reduced Drive Register 0 (RDR0AD1)
Port AD1 Reduced Drive Register 1 (RDR1AD1)
Port AD1 Pull Up Enable Register 0 (PER0AD1)
Port AD1 Pull Up Enable Register 1 (PER1AD1)
Table 24-2. PIM Memory Map (Sheet 3 of 3)
Use
Section 24.0.5, “Regis-
Read / Write
Read / Write
Read / Write
Read / Write
Read / Write
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Read / Write
Read / Write
Read / Write
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Read / Write
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Read / Write
Read / Write
Read / Write
Access
Read
1
1
1
1
1
1
1

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