C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 166

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201
C8051F020/1/2/3
17.1.7. External Memory Interface Pin Assignments
If the External Memory Interface (EMIF) is enabled on the Low ports (Ports 0 through 3), EMIFLE (XBR2.1) should
be set to a logic 1 so that the Crossbar will not assign peripherals to P0.7 (/WR), P0.6 (/RD), and if the External Mem-
ory Interface is in Multiplexed mode, P0.5 (ALE). Figure 17.4 shows an example Crossbar Decode Table with
EMIFLE=1 and the EMIF in Multiplexed mode. Figure 17.5 shows an example Crossbar Decode Table with
EMIFLE=1 and the EMIF in Non-multiplexed mode.
If the External Memory Interface is enabled on the Low ports and an off-chip MOVX operation occurs, the External
Memory Interface will control the output states of the affected Port pins during the execution phase of the MOVX
instruction, regardless of the settings of the Crossbar registers or the Port Data registers. The output configuration of
the Port pins is not affected by the EMIF operation, except that Read operations will explicitly disable the output
drivers on the Data Bus. See
XRAM” on page 145
166
TX0
RX0
SCK
MISO
MOSI
NSS
SDA
SCL
TX1
RX1
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
CP0
CP1
T0
/INT0
T1
/INT1
T2
T2EX
T4
T4EX
/SYSCLK
CNVSTR
PIN I/O 0
    
    
    
    
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    
    
    
1
2
3
P0
EMIFLE = 1; EMIF in Multiplexed Mode; P1MDIN = 0xFF)
4
5
for more information about the External Memory Interface.
6
7
Figure 17.4. Priority Crossbar Decode Table
       
       
       
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       
       
0
AIN1 Inputs/Non-muxed Addr H Muxed Addr H/Non-muxed Addr L
Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP
1
  
    
     
2
  
    
    
3
P1
4
5
6
7
 
  
   
    
     
      
       
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         
          
           
            
             
              
0
Rev. 1.4
1
2
3
P2
4
5
6
7
0
Muxed Data/Non-muxed Data
1
2
3
P3
4
5
6
7
Crossbar Register Bits
UART0EN:
UART1EN:
SMB0EN:
PCA0ME:
SYSCKE: XBR1.7
CNVSTE: XBR2.0
SPI0EN:
T2EXE: XBR1.6
T4EXE: XBR2.4
ECI0E: XBR0.6
INT0E: XBR1.2
INT1E: XBR1.4
CP0E: XBR0.7
CP1E: XBR1.0
T0E: XBR1.1
T1E: XBR1.3
T2E: XBR1.5
T4E: XBR2.3
XBR0.2
XBR0.1
XBR0.0
XBR2.2
XBR0.[5:3]

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