C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 177

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201
17.2. Ports 4 through 7 (C8051F020/2 only)
All Port pins on Ports 4 through 7 can be accessed as General-Purpose I/O (GPIO) pins by reading and writing the
associated Port Data registers (See Figure 17.21, Figure 17.22, Figure 17.23, and Figure 17.24), a set of SFRs which
are byte-addressable.
A Read of a Port Data register (or Port bit) will always return the logic state present at the pin itself, regardless of
whether the Crossbar has allocated the pin for peripheral use or not. An exception to this occurs during the execution
of a read-modify-write instruction (ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC, CLR, SET, and the bitwise MOV
operation). During the read cycle of the read-modify-write instruction, it is the contents of the Port Data register, not
the state of the Port pins themselves, which is read.
17.2.1. Configuring Ports which are not Pinned Out
Although P4, P5, P6, and P7 are not brought out to pins on the C8051F021/3 devices, the Port Data registers are still
present and can be used by software. Because the digital input paths also remain active, it is recommended that these
pins not be left in a ‘floating’ state in order to avoid unnecessary power dissipation arising from the inputs floating to
non-valid logic levels. This condition can be prevented by any of the following:
17.2.2. Configuring the Output Modes of the Port Pins
The output mode of each port pin can be configured to be either Open-Drain or Push-Pull. In the Push-Pull configura-
tion, a logic 0 in the associated bit in the Port Data register will cause the Port pin to be driven to GND, and a logic 1
will cause the Port pin to be driven to VDD. In the Open-Drain configuration, a logic 0 in the associated bit in the
Bit7:
Bit6:
Bits5-4:
Bit3:
Bit2:
Bits1-0:
R/W
IE7
Bit7
1.
2.
3.
IE7: External Interrupt 7 Pending Flag
0: No falling edge has been detected on P3.7 since this bit was last cleared.
1: This flag is set by hardware when a falling edge on P3.7 is detected.
IE6: External Interrupt 6 Pending Flag
0: No falling edge has been detected on P3.6 since this bit was last cleared.
1: This flag is set by hardware when a falling edge on P3.6 is detected.
UNUSED. Read = 00b, Write = don’t care.
IE7CF: External Interrupt 7 Edge Configuration
0: External Interrupt 7 triggered by a falling edge on the IE7 input.
1: External Interrupt 7 triggered by a rising edge on the IE7 input.
IE6CF: External Interrupt 6 Edge Configuration
0: External Interrupt 6 triggered by a falling edge on the IE6 input.
1: External Interrupt 6 triggered by a rising edge on the IE6 input.
UNUSED. Read = 00b, Write = don’t care.
Leave the weak pull-up devices enabled by setting WEAKPUD (XBR2.7) to a logic 0.
Configure the output modes of P4, P5, P6, and P7 to “Push-Pull” by writing P74OUT = 0xFF.
Force the output states of P4, P5, P6, and P7 to logic 0 by writing zeros to the Port Data regis-
ters: P4 = 0x00, P5 = 0x00, P6= 0x00, and P7 = 0x00.
R/W
IE6
Bit6
Figure 17.19. P3IF: Port3 Interrupt Flag Register
Bit5
R
-
Bit4
R
-
IE7CF
R/W
Bit3
Rev. 1.4
IE6CF
R/W
Bit2
C8051F020/1/2/3
R/W
Bit1
-
R/W
Bit0
-
SFR Address:
00000000
Reset Value
0xAD
177

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