C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 193

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201
18.4.3. Data Register
The SMBus0 Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received.
Software can read or write to this register while the SI flag is set to logic 1; software should not attempt to access the
SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0 since the hardware may be in the
process of shifting a byte of data in or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received data is
located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously being shifted in.
Therefore, SMB0DAT always contains the last data byte present on the bus. In the event of lost arbitration, the transi-
tion from master transmitter to slave receiver is made with the correct data in SMB0DAT.
18.4.4. Address Register
The SMB0ADR Address register holds the slave address for the SMBus0 interface. In slave mode, the seven most-
significant bits hold the 7-bit slave address. The least significant bit (Bit0) is used to enable the recognition of the
general call address (0x00). If Bit0 is set to logic 1, the general call address will be recognized. Otherwise, the general
call address is ignored. The contents of this register are ignored when SMBus0 is operating in master mode.
Bits7-0:
Bits7-1:
Bit0:
SLV6
R/W
R/W
Bit7
Bit7
SMB0DAT: SMBus0 Data.
The SMB0DAT register contains a byte of data to be transmitted on the SMBus0 serial interface or a
byte that has just been received on the SMBus0 serial interface. The CPU can read from or write to
this register whenever the SI serial interrupt flag (SMB0CN.3) is set to logic 1. When the SI flag is
not set, the system may be in the process of shifting data in/out and the CPU should not attempt to
access this register.
SLV6-SLV0: SMBus0 Slave Address.
These bits are loaded with the 7-bit slave address to which SMBus0 will respond when operating as a
slave transmitter or slave receiver. SLV6 is the most significant bit of the address and corresponds to
the first bit of the address byte received.
GC: General Call Address Enable.
This bit is used to enable general call address (0x00) recognition.
0: General call address is ignored.
1: General call address is recognized.
SLV5
R/W
R/W
Bit6
Bit6
Figure 18.11. SMB0ADR: SMBus0 Address Register
Figure 18.10. SMB0DAT: SMBus0 Data Register
SLV4
R/W
R/W
Bit5
Bit5
SLV3
R/W
R/W
Bit4
Bit4
SLV2
R/W
R/W
Bit3
Bit3
Rev. 1.4
SLV1
R/W
R/W
Bit2
Bit2
SLV0
C8051F020/1/2/3
R/W
R/W
Bit1
Bit1
R/W
R/W
Bit0
GC
Bit0
SFR Address:
SFR Address:
00000000
00000000
Reset Value
Reset Value
0xC2
0xC3
193

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