C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 196

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201
C8051F020/1/2/3
196
Mode
Status
Code
0xA0
0xA8
0xB0
0xB8
0xC0
0xC8
0xD0
0x60
0x68
0x70
0x78
0x80
0x88
0x90
0x98
0x00
0xF8
Own slave address + W received. ACK trans-
mitted.
Arbitration lost in sending SLA + R/W as mas-
ter. Own address + W received. ACK transmit-
ted.
General call address received. ACK transmit-
ted.
Arbitration lost in sending SLA + R/W as mas-
ter. General call address received. ACK trans-
mitted.
Data byte received. ACK transmitted.
Data byte received. NACK transmitted.
Data byte received after general call address.
ACK transmitted.
Data byte received after general call address.
NACK transmitted.
STOP or repeated START received.
Own address + R received. ACK transmitted.
Arbitration lost in transmitting SLA + R/W as
master. Own address + R received. ACK
transmitted.
Data byte transmitted. ACK received.
Data byte transmitted. NACK received.
Last data byte transmitted (AA=0). ACK
received.
SCL Clock High Timer per SMB0CR timed out
Bus Error (illegal START or STOP)
Idle
Table 18.1. SMB0STA Status Codes and States
SMBus State
Rev. 1.4
Wait for data.
Save current data for retry when bus is
free. Wait for data.
Wait for data.
Save current data for retry when bus is
free.
Read SMB0DAT. Wait for next byte or
STOP.
Set STO to reset SMBus.
Read SMB0DAT. Wait for next byte or
STOP.
Set STO to reset SMBus.
No action necessary.
Load SMB0DAT with data to transmit.
Save current data for retry when bus is
free. Load SMB0DAT with data to trans-
mit.
Load SMB0DAT with data to transmit.
Wait for STOP.
Set STO to reset SMBus.
Set STO to reset SMBus.
Set STO to reset SMBus.
State does not set SI.
Typical Action

Related parts for C8051F021-GQ