C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 223
Manufacturer Part Number
IC 8051 MCU 64K FLASH 64TQFP
Silicon Laboratories Inc
Specifications of C8051F021-GQ
Program Memory Type
Program Memory Size
64KB (64K x 8)
Package / Case
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
A/D 8x8b, 8x12b; D/A 2x12b
-40°C ~ 85°C
Data Bus Width
Data Ram Size
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
Minimum Operating Temperature
- 40 C
8-ch x 8-bit or 8-ch x 12-bit
2-ch x 12-bit
No. Of I/o's
Ram Memory Size
No. Of Timers
No. Of Pwm Channels
Data Rom Size
A/d Bit Size
A/d Channels Available
Supply Voltage (max)
Supply Voltage (min)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
The function of these bits is determined by the SSTAT1 bit in register PCON.
If SSTAT1 is logic 1, these bits are UART1 status indicators as described in
If SSTAT1 is logic 0, these bits select the Serial Port Operation Mode as shown below.
SM01-SM11: Serial Port Operation Mode:
SM21: Multiprocessor Communication Enable.
If SSTAT1 is logic 1, this bit is a UART1 status indicator as described in
If SSTAT1 is logic 0, the function of this bit is dependent on the Serial Port Operation Mode.
Mode 0: No effect.
Mode 1: Checks for valid stop bit.
Modes 2 and 3: Multiprocessor Communications Enable.
REN1: Receive Enable.
This bit enables/disables the UART1 receiver.
0: UART1 reception disabled.
1: UART1 reception enabled.
TB81: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in Modes 2 and 3. It is not used
in Modes 0 and 1. Set or cleared by software as required.
RB81: Ninth Receive Bit.
The bit is assigned the logic level of the ninth bit received in Modes 2 and 3. In Mode 1, if SM21 is
logic 0, RB81 is assigned the logic level of the received stop bit. RB8 is not used in Mode 0.
TI1: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART1 (after the 8th bit in Mode 0, or
at the beginning of the stop bit in other modes). When the UART1 interrupt is enabled, setting this bit
causes the CPU to vector to the UART1 interrupt service routine. This bit must be cleared manually
RI1: Receive Interrupt Flag.
Set by hardware when a byte of data has been received by UART1 (as selected by the SM21 bit).
When the UART1 interrupt is enabled, setting this bit causes the CPU to vector to the UART1 inter-
rupt service routine. This bit must be cleared manually by software.
0: Logic level of stop bit is ignored.
1: RI1 will only be activated if stop bit is logic level 1.
0: Logic level of ninth bit is ignored.
1: RI1 is set and an interrupt is generated only when the ninth bit is logic 1 and the received
address matches the UART1 address or the broadcast address.
Figure 21.8. SCON1: UART1 Control Register
Mode 1: 8-Bit UART, Variable Baud Rate
Mode 3: 9-Bit UART, Variable Baud Rate
Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 0: Synchronous Mode