C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 250

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201
C8051F020/1/2/3
23.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the
16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H
into a “snapshot” register; the following PCA0H read accesses this “snapshot” register. Reading the PCA0L Register
first guarantees an accurate reading of the entire 16-bit PCA0 counter. Reading PCA0H or PCA0L does not disturb
the counter operation. The CPS2-CPS0 bits in the PCA0MD register select the timebase for the counter/timer as
shown in Table 23.1. Note that in ‘External oscillator source divided by 8’ mode, the external oscillator source
is synchronized with the system clock, and must have a frequency less than or equal to the system clock.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to
logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in PCA0MD to logic 1
enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the
CPU vectors to the interrupt service routine, and must be cleared by software (Note: PCA0 interrupts must be glob-
ally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit (IE.7)
and the EPCA0 bit in EIE1 to logic 1). Clearing the CIDL bit in the PCA0MD register allows the PCA to continue
normal operation while the CPU is in Idle mode.
250
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
External oscillator source divided by 8 is synchronized with the system clock.
The minimum high or low time for the ECI input signal is at least 2 system clock cycles.
CPS2
0
0
0
0
1
1
C
D
L
I
W
D
T
E
PCA0MD
W
D
L
C
K
CPS1
C
P
S
0
0
1
1
0
0
2
000
001
010
011
100
101
C
P
S
1
C
P
S
0
E
C
F
Figure 23.2. PCA Counter/Timer Block Diagram
CPS0
IDLE
Table 23.1. PCA Timebase Input Options
0
1
0
1
0
1
C
F
C
R
PCA0CN
C
C
F
4
Timebase
High-to-low transitions on ECI
C
C
F
3
C
C
F
2
C
C
F
1
C
C
F
0
0
1
Rev. 1.4
PCA0L
External oscillator source divided by 8
read
System clock divided by 12
System clock divided by 4
Snapshot
Register
PCA0H
Timer 0 overflow
System clock
(max rate = system clock divided by 4)
PCA0L
To SFR Bus
To PCA Modules
Overflow
CF
To PCA Interrupt System

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