C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 265

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201

Available stocks

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24.
Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-system testing,
Flash read/write operations, and non-intrusive in-circuit debug. The JTAG interface is fully compliant with the IEEE
1149.1 specification. Refer to this specification for detailed descriptions of the Test Interface and Boundary-Scan
Architecture. Access of the JTAG Instruction Register (IR) and Data Registers (DR) are as described in the Test
Access Port and Operation of the IEEE 1149.1 specification.
The JTAG interface is accessed via four dedicated pins on the MCU: TCK, TMS, TDI, and TDO.
Through the 16-bit JTAG Instruction Register (IR), any of the seven instructions shown in Figure 24.1 can be com-
manded. There are three DR’s associated with JTAG Boundary-Scan, and four associated with Flash read/write oper-
ations on the MCU.
Bit15
IR Value
0xFFFF
0x0000
0x0002
0x0004
0x0082
0x0083
0x0084
JTAG (IEEE 1149.1)
Flash Address
Flash Control
PRELOAD
Instruction
SAMPLE/
Flash Data
EXTEST
IDCODE
BYPASS
Figure 24.1. IR: JTAG Instruction Register
Selects the Boundary Data Register for control and observability of all device pins
Selects FLASHADR Register which holds the address of all Flash read, write, and
Selects FLASHCON Register to control how the interface logic responds to reads
Selects the Boundary Data Register for observability and presetting the scan-path
Selects FLASHDAT Register for reads and writes to the Flash memory
and writes to the FLASHDAT Register
Selects Bypass Data Register
Rev. 1.4
Selects device ID Register
erase operations
Description
latches
C8051F020/1/2/3
Bit0
Reset Value
0x0000
265

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