C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 45

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201
5.2.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is
continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0 operates in low-
power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks (after
the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking mode,
ADC0 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 5.3). Track-
ing can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes. Low-power track-
and-hold mode is also useful when AMUX or PGA settings are frequently changed, to ensure that settling time
requirements are met (see
Timer 2, Timer 3 Overflow;
(AD0STM[1:0]=00, 01, 11)
Write '1' to AD0BUSY
(AD0STM[1:0]=10
SAR Clocks
SAR Clocks
SAR Clocks
ADC0TM=1
ADC0TM=0
ADC0TM=1
ADC0TM=0
CNVSTR
Figure 5.3. 12-Bit ADC Track and Conversion Example Timing
)
A. ADC Timing for External Trigger Source
B. ADC Timing for Internal Trigger Sources
Section “5.2.3. Settling Time Requirements” on page
Low Power
Low Power
or Convert
or Convert
Track or
Convert
Track Or Convert
1
1
Track
2
2
Track
3
3
4
4
1
5
5
2
6
6
3
7
7
Convert
4
8
8
Rev. 1.4
5
9
9
10 11 12 13 14 15 16 17 18 19
10 11 12 13 14 15 16
6
Convert
7
Convert
Convert
8
9
10 11 12 13 14 15 16
46).
C8051F020/1
Low Power Mode
Track
Low Power Mode
Track
45

Related parts for C8051F021-GQ