C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 50
Manufacturer Part Number
IC 8051 MCU 64K FLASH 64TQFP
Silicon Laboratories Inc
Specifications of C8051F021-GQ
Program Memory Type
Program Memory Size
64KB (64K x 8)
Package / Case
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
A/D 8x8b, 8x12b; D/A 2x12b
-40°C ~ 85°C
Data Bus Width
Data Ram Size
Maximum Clock Frequency
Number Of Programmable I/os
Number Of Timers
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
Minimum Operating Temperature
- 40 C
8-ch x 8-bit or 8-ch x 12-bit
2-ch x 12-bit
No. Of I/o's
Ram Memory Size
No. Of Timers
No. Of Pwm Channels
Data Rom Size
A/d Bit Size
A/d Channels Available
Supply Voltage (max)
Supply Voltage (min)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
AD0TM: ADC Track Mode Bit
0: When the ADC is enabled, tracking is continuous unless a conversion is in process
1: Tracking Defined by ADSTM1-0 bits
AD0INT: ADC0 Conversion Complete Interrupt Flag.
This flag must be cleared by software.
0: ADC0 has not completed a data conversion since the last time this flag was cleared.
1: ADC0 has completed a data conversion.
AD0BUSY: ADC0 Busy Bit.
0: ADC0 Conversion is complete or a conversion is not currently in progress. AD0INT is set to
logic 1 on the falling edge of AD0BUSY.
1: ADC0 Conversion is in progress.
0: No Effect.
1: Initiates ADC0 Conversion if AD0STM1-0 = 00b
AD0CM1-0: ADC0 Start of Conversion Mode Select.
If AD0TM = 0:
00: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
01: ADC0 conversion initiated on overflow of Timer 3.
10: ADC0 conversion initiated on rising edge of external CNVSTR.
11: ADC0 conversion initiated on overflow of Timer 2.
If AD0TM = 1:
00: Tracking starts with the write of ‘1’ to AD0BUSY and lasts for 3 SAR clocks, followed by con-
01: Tracking started by the overflow of Timer 3 and last for 3 SAR clocks, followed by conversion.
10: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge.
11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks, followed by conversion.
AD0WINT: ADC0 Window Compare Interrupt Flag.
This bit must be cleared by software.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
AD0LJST: ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Figure 5.8. ADC0CN: ADC0 Control Register (C8051F020/1)
AD0INT AD0BUSY AD0CM1 AD0CM0