C8051F021-GQ Silicon Laboratories Inc, C8051F021-GQ Datasheet - Page 76

IC 8051 MCU 64K FLASH 64TQFP

C8051F021-GQ

Manufacturer Part Number
C8051F021-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F021-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
No. Of Pwm Channels
5
Rohs Compliant
Yes
Data Rom Size
64 KB
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.05 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1201
C8051F020/1/2/3
7.2.
ADC1 has a maximum conversion speed of 500 ksps. The ADC1 conversion clock (SAR1 clock) is a divided version
of the system clock, determined by the AD1SC bits in the ADC1CF register (system clock divided by (AD1SC + 1)
for 0  AD1SC 31). The maximum ADC1 conversion clock is 6 MHz.
7.2.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC1 Start of Conver-
sion Mode bits (AD1CM2-0) in register ADC1CN. Conversions may be initiated by:
During conversion, the AD1BUSY bit is set to logic 1 and restored to 0 when conversion is complete. The falling
edge of AD1BUSY triggers an interrupt (when enabled) and sets the interrupt flag in ADC1CN. Converted data is
available in the ADC1 data word, ADC1.
When a conversion is initiated by writing a ‘1’ to AD1BUSY, it is recommended to poll AD1INT to determine when
the conversion is complete. The recommended procedure is:
7.2.2. Tracking Modes
The AD1TM bit in register ADC1CN controls the ADC1 track-and-hold mode. In its default state, the ADC1 input is
continuously tracked, except when a conversion is in progress. When the AD1TM bit is logic 1, ADC1 operates in
low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking period of 3 SAR clocks
(after the start-of-conversion signal). When the CNVSTR signal is used to initiate conversions in low-power tracking
mode, ADC1 tracks only when CNVSTR is low; conversion begins on the rising edge of CNVSTR (see Figure 7.2).
Tracking can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes. Low-power
Track-and-Hold mode is also useful when AMUX or PGA settings are frequently changed, due to the settling time
requirements described in
76
ADC1 Modes of Operation
1.
2.
3.
4.
5.
single software command). 
Step 1. Write a ‘0’ to AD1INT;
Step 2. Write a ‘1’ to AD1BUSY;
Step 3. Poll AD1INT for ‘1’;
Step 4. Process ADC1 data.
Writing a ‘1’ to the AD1BUSY bit of ADC1CN;
A Timer 3 overflow (i.e. timed continuous conversions);
A rising edge detected on the external ADC convert start signal, CNVSTR;
A Timer 2 overflow (i.e. timed continuous conversions);
Writing a ‘1’ to the AD0BUSY of register ADC0CN (initiate conversion of ADC1 and ADC0 with a
Section “7.2.3. Settling Time Requirements” on page
Rev. 1.4
78.

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