DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 116
DF2117VLP20V
Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VBG20V.pdf
(960 pages)
Specifications of DF2117VLP20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 116 of 960
- Download datasheet (6Mb)
Section 3 MCU Operating Modes
Rev. 3.00 Sep. 28, 2009 Page 70 of 910
REJ09B0350-0300
Bit
1
0
Bit Name
KINWUE
RAME
Initial
Value
0
1
R/W
R/W
R/W
Description
Keyboard Control Register Access Enable
When the RELOCATE bit is cleared to 0, this bit
enables or disables CPU access for the keyboard
matrix interrupt registers (KMIMRA and KMIMR), pull-
up MOS control register (KMPCR), and registers
(TCR_X/TCR_Y, TCSR_X/TCSR_Y, TICRR/TCORA_Y,
TICRF/TCORB_Y, TCNT_X/TCNT_Y, TCORC,
TCORA_X, TCORB_X, TCONRI, and TCONRS) of 8-bit
timers (TMR_X and TMR_Y)
0: Enables CPU access for registers of TMR_X and
1: Enables CPU access for the keyboard matrix
When the RELOCATE bit is set to 1, this bit is disabled.
For details, see section 3.2.4, System Control Register
3 (SYSCR3) and section 25, List of Registers.
RAM Enable
Enables or disables on-chip RAM.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
TMR_Y in areas from H'(FF)FFF0 to H'(FF)FFF7 and
from H'(FF)FFFC to H'(FF)FFFF
interrupt registers and input pull-up MOS control
register in areas from H'(FF)FFF0 to H'(FF)FFF7 and
from H'(FF)FFFC to H'(FF)FFFF
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