DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 131
DF2117VLP20V
Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VBG20V.pdf
(960 pages)
Specifications of DF2117VLP20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 131 of 960
- Download datasheet (6Mb)
5.1
• Two interrupt control modes
• Priorities settable with ICR
• Three-level interrupt mask control
• Forty-one external interrupt pins
• Two interrupt vector addresses are selectable
• General ports for IRQ15 to IRQ6 input are selectable
Two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system
control register (SYSCR).
An interrupt control register (ICR) is provided for setting in each module interrupt priority
levels for all interrupt requests excluding NMI and address breaks.
By means of the interrupt control mode, I and UI bits in CCR and ICR, 3-level interrupt mask
control is performed.
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling-edge, rising-edge, or both-edge detection, or level
sensing, can be independently selected for IRQ15 to IRQ0. When the EIVS bit in the system
control register 3 (SYSCR3) is cleared to 0, the IRQ6 interrupt is generated by IRQ6 or KIN7
to KIN0. The IRQ7 interrupt is generated by IRQ7 or KIN15 to KIN8. When the EIVS bit in
the system control register 3 (SYSCR3) is set to 1, interrupts are requested on the falling edge
of KIN15 to KIN0. For WUE15 to WUE8, either rising-edge or falling-edge detection can be
selected individually for each pin regardless of the EIVS bit setting.
H8S/2140B Group compatible interrupt vector addresses or extended interrupt vector
addresses are selected depending on the EIVS bit in system control register 3 (SYSCR3). In
extended mode, independent vector addresses are assigned for the interrupt vector addresses of
KIN7 to KIN0 or KIN15 to KIN8 interrupts.
Features
Section 5 Interrupt Controller
Rev. 3.00 Sep. 28, 2009 Page 85 of 910
Section 5 Interrupt Controller
REJ09B0350-0300
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