DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 346
DF2117VLP20V
Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VBG20V.pdf
(960 pages)
Specifications of DF2117VLP20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Section 10 16-Bit Timer Pulse Unit (TPU)
10.8.7
If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read
will be the data after input capture transfer. Figure 10.48 shows the timing in this case.
Rev. 3.00 Sep. 28, 2009 Page 300 of 910
REJ09B0350-0300
Figure 10.47 Conflict between Buffer Register Write and Compare Match
Conflict between TGR Read and Input Capture
φ
Address
Read signal
Input capture
signal
TGR
Internal
data bus
φ
Address
Write signal
Compare
match signal
Buffer
register
TGR
Figure 10.48 Conflict between TGR Read and Input Capture
X
TGR read cycle
N
TGR write cycle
TGR address
T1
Buffer register
T1
address
M
T2
T2
M
M
N
Buffer register write data
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