DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 495
DF2117VLP20V
Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VBG20V.pdf
(960 pages)
Specifications of DF2117VLP20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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15.7.2
Figure 15.22 shows the data transfer formats in smart card interface mode.
• One frame contains 8-bit data and a parity bit in asynchronous mode.
• During transmission, at least 2 etu (elementary time unit: time required for transferring one bit)
• If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu
• If an error signal is sampled during transmission, the same data is automatically re-transmitted
For communication with the IC cards of the direct convention and inverse convention types,
follow the procedure below.
is secured as a guard time after the end of the parity bit before the start of the next frame.
has passed from the start bit.
after two or more etu.
Data Format (Except in Block Transfer Mode)
Figure 15.22 Data Formats in Normal Smart Card Interface Mode
In normal transmission/reception
When a parity error is generated
[Legend]
Ds:
D0 to D7 :
Dp:
DE:
(Z)
Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0)
Ds
Ds
Ds
A
Start bit
Data bits
Parity bit
Error signal
D0
D0
D0
Z
Output from the transmitting station
Output from the transmitting station
D1
D1
D1
Z
D2
D2
D2
A
D3
D3
D3
Z
D4
D4
D4
Z
D5
D5
D5
Z
D6
D6
D6
Section 15 Serial Communication Interface (SCI)
A
D7
D7
D7
A
Rev. 3.00 Sep. 28, 2009 Page 449 of 910
Dp
Dp
Dp
Z
Output from
the receiving station
(Z) state
DE
REJ09B0350-0300
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