DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 563
DF2117VLP20V
Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VBG20V.pdf
(960 pages)
Specifications of DF2117VLP20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 563 of 960
- Download datasheet (6Mb)
Bit
5
4
3
Bit Name
MST
TRS
ACKE
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
[MST clearing conditions]
1. When 0 is written by software
2. When lost in bus contention in I
[MST setting conditions]
1. When 1 is written by software (for MST clearing
2. When 1 is written in MST after reading MST = 0 (for
[TRS clearing conditions]
1. When 0 is written by software (except for TRS
2. When 0 is written in TRS after reading TRS = 1 (for
3. When lost in bus contention in I
[TRS setting conditions]
1. When 1 is written by software (except for TRS
2. When 1 is written in TRS after reading TRS = 0 (for
3. When 1 is received as the R/W bit after the first
0: The value of the acknowledge bit is ignored, and
1: If the received acknowledge bit is 1, continuous
Depending on the receiving device, the acknowledge
bit may be significant, in indicating completion of
processing of the received data, for instance, or may
be fixed at 1 and have no significance.
Acknowledge Bit Decision and Selection
continuous transfer is performed. The value of the
received acknowledge bit is not indicated by the
ACKB bit in ICSR, which is always 0.
transfer is halted.
master mode
condition 1)
MST clearing condition 2)
setting condition 3)
TRS setting condition 3)
master mode
clearing condition 3)
TRS clearing condition 3)
frame address matching in I
mode
Rev. 3.00 Sep. 28, 2009 Page 517 of 910
Section 17 I
2
C bus format slave
2
2
C bus format
C bus format
2
C Bus Interface (IIC)
REJ09B0350-0300
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