DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 605
DF2117VLP20V
Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VBG20V.pdf
(960 pages)
Specifications of DF2117VLP20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
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Company:
Part Number:
DF2117VLP20V
Manufacturer:
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Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
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6. Note on ICDR read in transmit mode and ICDR write in receive mode
7. Note on ACKE and TRS bits in slave mode
17.6.1
The IIC operation can be enabled or disabled using the module stop control register. The initial
setting is for the IIC operation to be halted. Register access is enabled by canceling module stop
mode. For details, see section 24, Power-Down Modes.
If ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0),
the SCL pin may not be held low in some cases after transmit/receive operation has been
completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before
ICDR is accessed correctly. To access ICDR correctly, read ICDR after setting receive mode
or write to ICDR after setting transmit mode.
In the I
mode (TRS = 1) and then the address is received in slave mode without performing appropriate
processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the
address does not match. Similarly, if the start condition or address is transmitted from the
master device in slave transmit mode (TRS = 1), the IRIC flag may be set after the ICDRE flag
is set and 1 received as the acknowledge bit value (ACKB = 1), thus causing an interrupt
source even when the address does not match.
To use the I
A. When having received 1 as the acknowledge bit value for the last transmit data at the end
B. Set receive mode (TRS = 0) before the next start condition is input in slave mode.
of a series of transmit operation, clear the ACKE bit in ICCR once to initialize the ACKB
bit to 0.
Complete transmit operation by the procedure shown in figure 17.16, in order to switch
from slave transmit mode to slave receive mode.
Module Stop Mode Setting
2
C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit
2
C bus interface module in slave mode, be sure to follow the procedures below.
Rev. 3.00 Sep. 28, 2009 Page 559 of 910
Section 17 I
2
C Bus Interface (IIC)
REJ09B0350-0300
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