DF2117VLP20V Renesas Electronics America, DF2117VLP20V Datasheet - Page 730
DF2117VLP20V
Manufacturer Part Number
DF2117VLP20V
Description
IC H8S/2117 MCU FLASH 145TFLGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheet
1.DF2117VBG20V.pdf
(960 pages)
Specifications of DF2117VLP20V
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
FIFO, I²C, LPC, SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
112
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
145-TFLGA
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2117VLP20V
Manufacturer:
Renesas
Quantity:
100
Part Number:
DF2117VLP20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Section 22 Flash Memory
There are several operating modes for accessing the flash memory. Respective operating modes,
registers, and parameters are assigned to the user MAT. The correspondence between operating
modes and registers/parameters for use is shown in table 22.5.
Table 22.5 Registers/Parameters and Target Modes
Notes: 1. Programming and erasure of the user MAT in user boot mode require settings.
22.7.1
The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes.
These registers are initialized by a power-on reset.
(1)
FCCS monitors errors during programming/erasing the flash memory and requests the on-chip
program to be downloaded to the on-chip RAM.
Rev. 3.00 Sep. 28, 2009 Page 684 of 910
REJ09B0350-0300
Register/Parameter
Programming/
erasing interface
registers
Programming/
erasing interface
parameters
Flash Code Control/Status Register (FCCS)
2. A setting may be required depending on the combination of the startup mode and the
Programming/Erasing Interface Registers
MAT to be read.
FCCS
FPCS
FECS
FKEY
FMATS
FTDAR
DPFR
FPFR
FPEFEQ
FMPAR
FMPDR
FEBS
O
O
O
O
⎯
O
O
⎯
⎯
⎯
⎯
⎯
Download
Initiali-
zation
⎯
⎯
⎯
⎯
⎯
⎯
⎯
O
O
⎯
⎯
⎯
Program-
ming
⎯
⎯
⎯
O
O*
⎯
⎯
O
⎯
O
O
⎯
1
Erasure
⎯
⎯
⎯
O
O*
⎯
⎯
O
⎯
⎯
⎯
O
1
Read
⎯
⎯
⎯
⎯
O*
⎯
⎯
⎯
⎯
⎯
⎯
⎯
2
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