MC9S12XDT512CAG Freescale Semiconductor, MC9S12XDT512CAG Datasheet - Page 753
MC9S12XDT512CAG
Manufacturer Part Number
MC9S12XDT512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12XD64CAA.pdf
(1348 pages)
Specifications of MC9S12XDT512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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20.3.2.4
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
Freescale Semiconductor
Address: 0x0023
CDCM[1:0]
ABCM[1:0]
Reset
Field
3–2
1–0
W
R
CDCM
ABCM
00
01
10
11
00
01
10
11
C and D Comparator Match Control — These bits determine the C and D comparator match mapping as
described in
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
described in
Debug Control Register2 (DBGC2)
0
0
7
= Unimplemented or Reserved
Match2 mapped to comparator C match....... Match3 mapped to comparator D match.
Match0 mapped to comparator A match....... Match1 mapped to comparator B match.
Table
Table
0
0
6
20-14.
20-15.
Match 0 mapped to comparator A/B outside range....... Match1 disabled.
Match2 mapped to comparator C/D outside range....... Match3 disabled.
Match 0 mapped to comparator A/B inside range....... Match1 disabled.
Match2 mapped to comparator C/D inside range....... Match3 disabled.
Figure 20-6. Debug Control Register2 (DBGC2)
Table 20-13. DBGC2 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
Table 20-14. CDCM Encoding
Table 20-15. ABCM Encoding
0
0
4
Description
Description
Description
Reserved
Reserved
0
3
CDCM
Chapter 20 S12X Debug (S12XDBGV3) Module
0
2
0
1
ABCM
0
0
755
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