DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 131
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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2.2.31 (2)
EXTU (EXTend as Unsigned)
Operation
0
Assembly-Language Format
EXTU.L ERd
Operand Size
Longword
Description
This instruction extends the lower 16 bits (general register Rd) in a 32-bit register ERd to
longword data by padding with zeros. That is, it clears the upper 16 bits of ERd (bits 31 to 16) to
0.
Available Registers
ERd: ER0 to ER7
Operand Format and Number of States Required for Execution
Notes
Register direct
Addressing
(<bits 31 to 16> of ERd)
Mode
Bit 31
EXTU (L)
Don’t care
16 bits
Mnemonic
EXTU.L
ERd
15
Operands
16 bits
ERd
1st byte
1
0
7
Condition Code
H: Previous value remains unchanged.
N: Always cleared to 0.
Z: Set to 1 if the result is zero; otherwise
V: Always cleared to 0.
C: Previous value remains unchanged.
Bit 31
2nd byte
7
Instruction Format
cleared to 0.
Zero extension
Rev. 4.00 Feb 24, 2006 page 115 of 322
—
I
0 erd
UI H
—
16 bits
Section 2 Instruction Descriptions
—
3rd byte
ERd
—
U
15
N
0
16 bits
4th byte
REJ09B0139-0400
Z
Zero Extension
V
0
—
0
States
No. of
C
1
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