DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 123
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4.1
As table 4.1 indicates, exception handling is caused by a reset, a trace, an address error, an
interrupt, a trap instruction, and an illegal instruction (general illegal instruction or slot illegal
instruction). Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Exception sources, the
stack structure, and operation of the CPU vary depending on the interrupt control mode. For
details on the interrupt control mode, see section 5, Interrupt Controller.
Table 4.1
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
Priority
High
Low
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
3. Trap instruction exception handling requests are accepted at all times in program
Exception Handling Types and Priority
Exception Type
Reset
Illegal instruction
Trace*
Address error
Interrupt
Trap instruction*
executed after execution of an RTE instruction.
instruction execution, or on completion of reset exception handling.
execution state.
Exception Types and Priority
1
Section 4 Exception Handling
3
Exception handling starts when an undefined code is
After an address error has occurred, exception handling
Exception handling starts after execution of the current
Exception handling starts by execution of a trap instruction
Exception Handling Start Timing
Exception handling starts at the timing of level change from
low to high on the RES pin, or when the watchdog timer
overflows. The CPU enters the reset state when the RES
pin is low.
executed.
Exception handling starts after execution of the current
instruction or exception handling, if the trace (T) bit in EXR
is set to 1.
starts on completion of instruction execution.
instruction or exception handling, if an interrupt request has
occurred.*
(TRAPA).
2
Rev.1.00 Sep. 08, 2005 Page 73 of 966
Section 4 Exception Handling
REJ09B0219-0100
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