DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 249
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.9.4
Table 6.19 shows the pins used for the address/data multiplexed I/O Interface.
Table 6.19 I/O Pins for Address/Data Multiplexed I/O Interface
Note:
Pin
CSn
AS/AH
RD
LHWR/LUB
LLWR/LLB
D15 to D0
A20 to A0
WAIT
BS
RD/WR
*
I/O Pins Used for Address/Data Multiplexed I/O Interface
The AH output is multiplexed with the AS output. At the timing that an area is specified
as address/data multiplexed I/O, this pin starts to function as the AH output meaning
that this pin cannot be used as the AS output. At this time, when other areas set to the
basic bus interface is accessed, this pin does not function as the AS output. Until an
area is specified as address/data multiplexed I/O, be aware that this pin functions as
the AS output.
When Byte
Control
SRAM is
Specified
CSn
AH*
RD
LHWR
LLWR
D15 to D0
A20 to A0
WAIT
BS
RD/WR
Name
Chip select
Address hold
Read strobe
Low-high write Output
Low-low write Output
Address/data
Address
Wait
Bus cycle start Output
Read/write
I/O
Output
Output
Output
Input/
output
Output
Input
Output
Function
Address output pin
Wait request signal used when the external address
Chip select (n = 3 to 7) when area n is specified as the
address/data multiplexed I/O space
Signal to hold an address when the address/data
multiplexed I/O space is specified
Signal indicating that the address/data multiplexed I/O
space is being read
Strobe signal indicating that the upper byte (D15 to
D8) is valid when the address/data multiplexed I/O
space is written
Strobe signal indicating that the lower byte (D7 to D0)
is valid when the address/data multiplexed I/O space is
written
Address and data multiplexed pins for the
address/data multiplexed I/O space.
Only D7 to D0 are valid when the 8-bit space is
specified. D15 to D0 are valid when the 16-bit space is
specified.
space is accessed
Signal to indicate the bus cycle start
Signal indicating the data bus input or output direction
Rev.1.00 Sep. 08, 2005 Page 199 of 966
Section 6 Bus Controller (BSC)
REJ09B0219-0100
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