DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 253
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
DF61654N50FTV
Manufacturer:
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Quantity:
10 000
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6.9.7
In the data cycle of the address/data multiplexed I/O interface, program wait insertion and pin wait
insertion by the WAIT pin are enabled in the same way as in the basic bus interface. For details,
refer to section 6.6.4, Wait Control.
Wait control settings do not affect the address cycles.
6.9.8
In the address/data multiplexed I/O interface, the read strobe timing of data cycles can be modified
in the same way as in basic bus interface. For details, refer to section 6.6.5, Read Strobe (RD)
Timing.
Figure 6.33 shows an example when the read strobe timing is modified.
Wait Control
Read Strobe (RD) Timing
Rev.1.00 Sep. 08, 2005 Page 203 of 966
Section 6 Bus Controller (BSC)
REJ09B0219-0100
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