DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 345
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(4)
Figure 7.37 shows an example of normal transfer mode activated by the DREQ signal low level.
The DREQ signal is sampled every cycle from the next rising edge of the Bφ signal immediately
after the DTE bit write cycle.
When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is
enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer
request is cleared. Receiving the next transfer request resumes after completion of the single cycle
and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is
completed.
[1]
[2][5] The DMAC is activated and the transfer request is cleared.
[3][6] A DMA cycle is started.
[4][7] Transfer request enable is resumed after completion of the single cycle.
Activation Timing by DREQ Low Level
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer
request is held.
(A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].)
B
DREQ
Address bus
DACK
DMA
operation
Channel
Figure 7.37 Example of Transfer in Single Address Mode Activated
Wait
[1]
Request
Min. of 3 cycles
released
[2]
Bus
Duration of transfer
request disabled
Single
by DREQ Low Level
[3]
Transfer destination
Transfer source/
DMA single
Wait
cycle
Transfer request
enable resumed
[4]
Request
Min. of 3 cycles
[5]
released
Bus
Rev.1.00 Sep. 08, 2005 Page 295 of 966
Duration of transfer
request disabled
Single
Section 7 DMA Controller (DMAC)
[6]
Transfer destination
Transfer source/
DMA single
cycle
Wait
Transfer request
enable resumed
[7]
released
Bus
REJ09B0219-0100
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