DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 459
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
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Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 10.12 MD3 to MD0
[Legend]
X: Don't care
Notes: 1. MD3 is a reserved bit. The write value should always be 0.
10.3.3
TIOR controls TGR. The TPU has eight TIOR registers, two each for channels 0 and 3, and one
each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
To designate the input capture pin in TIOR, the DDR bit and ICR bit for the corresponding pin
should be set to 0 and 1, respectively. For details, see section 9, I/O Ports.
Bit 3
MD3*
0
0
0
0
0
0
0
0
1
1
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
Timer I/O Control Register (TIOR)
Bit 2
MD2*
0
0
0
0
1
1
1
1
X
be written to MD2.
2
Bit 1
MD1
0
0
1
1
0
0
1
1
X
Bit 0
MD0
0
1
0
1
0
1
0
1
X
Description
Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.1.00 Sep. 08, 2005 Page 409 of 966
REJ09B0219-0100
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