DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 611
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 611 of 1020
- Download datasheet (6Mb)
Note:
14.3.7
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in
normal mode and smart card interface mode.
• When SMIF in SCMR = 0
Bit
1
0
Note: * Only 0 can be written, to clear the flag.
Bit
Bit Name
Initial Value
R/W
*
Bit Name
CKE1
CKE0
Serial Status Register (SSR)
No SCK pins exist in SCI_5 and SCI_6.
R/(W)*
TDRE
7
1
Initial
Value
0
0
R/(W)*
RDRF
6
0
R/W
R/W
R/W
R/(W)*
ORER
5
0
Description
Clock Enable 1, 0*
These bits control the clock output from the SCK pin. In
GSM mode, clock output can be dynamically switched.
For details, see section 14.7.8, Clock Output Control.
•
00: Output disabled (SCK pin functions as I/O port.) *
01: Clock output
1X: Reserved
•
00: Output fixed low
01: Clock output
10: Output fixed high
11: Clock output
Section 14 Serial Communication Interface (SCI, IrDA, CRC)
When GM in SMR = 0
When GM in SMR = 1
R/(W)*
FRE
4
0
R/(W)*
PER
3
0
Rev.1.00 Sep. 08, 2005 Page 561 of 966
TEND
R
2
1
MPB
R
1
0
REJ09B0219-0100
MPBT
R/W
0
0
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