DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 768
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 16 I
16.4
16.4.1
Figure 16.3 shows the I
following a start condition always consists of 8 bits.
(a) I
(b) I
[Legend]
S:
SLA:
R/W:
A:
DATA: Transferred data
P:
Rev.1.00 Sep. 08, 2005 Page 718 of 966
REJ09B0219-0100
SDA
SCL
2
2
C bus format
C bus format (start condition retransmission)
S
S
1
1
S
Start condition. The master device drives SDA from high to low while SCL is high.
Slave address
Indicates the direction of data transfer; from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
Acknowledge. The receive device drives SDA low.
Stop condition. The master device drives SDA from low to high while SCL is high.
Operation
I
2
2
C Bus Format
C Bus Interface2 (IIC2)
SLA
SLA
7
7
SLA
1-7
1
1
R/W
R/W
1
1
2
C bus formats. Figure 16.4 shows the I
R/W
8
A
A
1
1
A
9
DATA
DATA
Figure 16.3 I
Figure 16.4 I
n1
n
m1
1-7
A
1
A/A
DATA
m
1
2
C Bus Formats
2
C Bus Timing
S
1
8
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2
SLA
A/A
9
A
1
7
2
C bus timing. The first frame
P
1
1
R/W
1
1-7
m: Transfer frame count
(m
n: Transfer bit count
(n = 1 to 8)
DATA
A
1
1)
8
DATA
n2
m2
A
9
A/A
1)
1
P
1
P
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