DF2338VFC25V Renesas Electronics America, DF2338VFC25V Datasheet - Page 174
DF2338VFC25V
Manufacturer Part Number
DF2338VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2338VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2338VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.2.5
BCRL is an 8-bit readable/writable register that performs selection of the external bus-released
state protocol, selection of the area partition unit, enabling or disabling of the write data buffer
function, and enabling or disabling of WAIT pin input.
BCRL is initialized to H'3C by a reset, and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.
Bit 7
BRLE
0
1
Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master
to drop the bus request signal (BREQ) in the external bus-released state, when an internal bus
master performs an external space access, or when a refresh request is generated.
Bit 6
BREQOE
0
1
Bit 5—External Address Enable (EAE): Designates addresses H'010000 to H'03FFFF *
either internal or external addresses.
Rev.4.00 Sep. 07, 2007 Page 142 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
Bus Control Register L (BCRL)
:
:
Description
External bus release disabled. BREQ, BACK, and BREQO pins can be used as I/O
ports
External bus release enabled
Description
BREQO output disabled. BREQO pin can be used as I/O port
BREQO output enabled
BRLE
R/W
7
0
BREQOE
R/W
6
0
EAE
R/W
5
1
R/W
—
4
1
DDS
R/W
1
3
R/W
—
2
1
WDBE
R/W
1
0
(Initial value)
(Initial value)
2
WAITE
as
R/W
0
0
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