M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 117

• Manufacturer Part Number: M30626FJPGP#U3C
• Description: IC M16C MCU FLASH 512K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 10.11
Main clock oscillation
NOTES:
PLL operation mode
CPU clock : f(PLL)
CPU clock : f(PLL)
1. Avoid making a transition when the CM20 bit in the CM2 register is set to “1” (oscillation stop, re-oscillation detection function enabled).
2. Wait the main clock oscillation stabilizes.
3. Switch clock after oscillation of sub-clock is sufficiently stable.
4. Change CM17 and CM16 bits in the CM1 register before changing CM06 bit in the CM0 register.
5. Transit in accordance with arrow.
6. The PM20 bit in the PM2 register become effective when the PLC07 bit in the PLC0 register is set to “1” (PLL on). Change the PM20 bit when the PLC07 bit is set to “0” (PLL off).
7. Set the CM06 bit to “1” (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode.
8. When the CM21 bit in the CM2 register = 0 (on-chip oscillator turned off) and the CM05 bit in the CM0 register = 1 (main clock turned off), the CM06 bit is fixed to 1 (divide-by-8 mode)
Sub clock oscillation
CM04=1
PLL operation
mode
Set the CM20 bit to “0” (oscillation stop, re-oscillation detection function disabled) before transiting.
Set the PM20 bit to “0” (2 waits) when PLL clock >16MHz.
and the CM15 bit in the CM1 register is fixed to “1” (drive capability High).
CM07=0
CM06=0
CM17=0
CM16=0
CM07=0
CM06=0
CM17=0
CM16=0
Jan 10, 2006
CM04=0
CM11=1
CM11=1
PLC07=1
PLC07=1
PLC07=0
CM11=0
PLC07=0
CM11=0
State Transition in Normal Operating Mode
(6)
(6)
CPU clock : f(XIN)
CPU clock : f(XIN)
High-speed mode
High-speed mode
CM07=0
CM06=0
CM17=0
CM16=0
CM07=0
CM06=0
CM17=0
CM16=0
Page 100 of 390
CPU clock : f(XIN)/2
CPU clock : f(XIN)/2
Middle-speed mode
Middle-speed mode
(divide by 2)
(divide by 2)
CM07=0
CM06=0
CM17=0
CM16=1
CM07=0
CM06=0
CM17=0
CM16=1
CM04=1
CM07=1
CM05=1
(3)
(1, 8)
Low power dissipation mode
CPU clock : f(XIN)/4
CPU clock : f(XIN)/4
CPU clock : f(XCIN)
Middle-speed mode
Middle-speed mode
CPU clock : (XCIN)
Low-speed mode
(divide by 4)
(divide by 4)
CM07=0
CM07=0
CM06=1
CM15=1
CM07=0
CM06=0
CM17=1
CM16=0
CM07=0
CM06=0
CM17=1
CM16=0
Middle-speed mode
CPU clock : f(XIN)/8
Middle-speed mode
CPU clock : f(XIN)/8
(divide by 8)
(divide by 8)
CM07=0
CM06=1
CM07=0
CM06=1
CM04=0
CM07=0
CM05=0
(2, 4)
CPU clock : f(XIN)/16
CPU clock : f(XIN)/16
Middle-speed mode
Middle-speed mode
(divide by 16)
(divide by 16)
CM07=0
CM06=0
CM17=1
CM16=1
CM07=0
CM06=0
CM17=1
CM16=1
CM21=0
CM21=1
CM21=0
CM21=0
CM21=1
CM21=1
(7)
(7)
On-chip oscillator mode
CPU clock : f(XCIN)
Low-speed mode
CM04=1
On-chip oscillator
mode
CPU clock
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM07=0
CM04=0
10. Clock Generation Circuit
CM05=1
CM05=1
CM05=0
CM05=0
(1)
(1)
On-chip oscillator clock oscillation
On-chip oscillator low power
dissipation mode
CM04=1
On-chip oscillator
low power
dissipation mode
CPU clock
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM04=0