M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 133

• Manufacturer Part Number: M30626FJPGP#U3C
• Description: IC M16C MCU FLASH 512K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 12.7
12.5.7
Address
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register,
16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved.
Figure 12.7 shows the Stack Status Before and After Acceptance of Interrupt Request.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use the
PUSHM instruction, and all registers except SP can be saved with a single instruction.
m − 4
m − 3
m − 2
m − 1
m
m + 1
Stack status before interrupt request
is acknowledged
MSB
Jan 10, 2006
PCH : 4 high-order bits of PC
PCM : 8 middle-order bits of PC
PCL
Saving Registers
Content of previous stack
Content of previous stack
: 8 low-order bits of PC
Stack Status Before and After Acceptance of Interrupt Request
Stack
Page 116 of 390
LSB
FLGH : 4 high-order bits of FLG
FLGL : 8 low-order bits of FLG
[SP]
SP value before
interrupt request is
accepted.
Address
m − 4
m − 3
m − 2
m − 1
m
m + 1
Stack status after interrupt request
is acknowledged
MSB
Content of previous stack
Content of previous stack
FLGH
Stack
FLGL
PCM
PCL
PCH
LSB
[SP]
New SP value
12. Interrupt