M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 206

IC M16C MCU FLASH 512K 100LQFP

M30626FJPGP#U3C

Manufacturer Part Number
M30626FJPGP#U3C
Description
IC M16C MCU FLASH 512K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets

Specifications of M30626FJPGP#U3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30626FJPGP#U3CM30626FJPGP
Manufacturer:
ATMEL
Quantity:
1
Company:
Part Number:
M30626FJPGP#U3CM30626FJPGP
Manufacturer:
MIT
Quantity:
1 000
Company:
Part Number:
M30626FJPGP#U3CM30626FJPGP
Manufacturer:
MIT
Quantity:
20 000
Company:
Part Number:
M30626FJPGP#U3CM30626FJPGP
Manufacturer:
RENESAS
Quantity:
9 423
Company:
Part Number:
M30626FJPGP#U3CM30626FJPGP U5C
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
17.1.1
Table 17.1
NOTES:
Transfer Data Format
Transfer Clock
Transmission, Reception
Control
Transmission Start
Condition
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0
2. If an overrun error occurs, the receive data of UiRB register will be indeterminate. The IR bit in the SiRIC
3. The U0IRS and U1IRS bits respectively are the bits 0 and 1 in the UCON register; the U2IRS bit is the bit 4 in
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 17.1 lists the
Clock Synchronous Serial I/O Mode Specifications. Table 17.2 lists the Registers to Be Used and Settings in
Clock Synchronous Serial I/O Mode.
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the external clock is in the high state; if the CKPOL bit in the UiC0 register = 1 (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
register does not change.
the U2C1 register.
Jan 10, 2006
Clock Synchronous Serial I/O Mode
Item
Clock Synchronous Serial I/O Mode Specifications
Page 189 of 390
Transfer data length: 8 bits
• CKDIR bit in the UiMR(i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1))
• CKDIR bit = 1 (external clock) : Input from CLKi pin
Selectable from CTS function, RTS function or CTS/RTS function disable
Before transmission can start, meet the following requirements
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
• If CTS function is selected, input on the CTSi pin = L
Before reception can start, meet the following requirements
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
For transmission, one of the following conditions can be selected
• The UiIRS bit
• The UiIRS bit =1 (transfer completed): when the serial interface finished sending data
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
Overrun error
• CLK polarity selection
• LSB first, MSB first selection
• Continuous receive mode selection
• Switching serial data logic
• Transfer clock output from multiple pins selection (UART1)
• Separate CTS/RTS pins (UART0)
register to the UARTi transmit register (at start of transmission)
from the UARTi transmit register
completion of reception)
fj = f1SIO, f2SIO, f8SIO, f32SIO
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the 7th bit of the next data
Transfer data input/output can be chosen to occur synchronously with the rising or the
falling edge of the transfer clock
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can
be selected
Reception is enabled immediately by reading the UiRB register
This function reverses the logic value of the transmit/receive data
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
CTS0 and RTS0 are input/output from separate pins
(2)
(3)
= 0 (transmit buffer empty): when transferring data from the UiTB
n: Setting value of UiBRG register
Specification
(1)
(1)
17. Serial Interface
00h to FFh

Related parts for M30626FJPGP#U3C