M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 210

• Manufacturer Part Number: M30626FJPGP#U3C
• Description: IC M16C MCU FLASH 512K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.14
17.1.1.1
17.1.1.2
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow
the procedures below.
Use the CKPOL bit in the UiC0 register (i = 0 to 2) to select the transfer clock polarity. Figure 17.14 shows the
Transfer Clock Polarity.
(1) When the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling
(2) When the CKPOL bit = 1 (transmit data output at the rising edge and the receive
CLKi
TXDi
RXDi
CLKi
TXDi
RXDi
•
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to “000b” (Serial interface disabled)
(3) Set the SMD2 to SMD0 bits in the UiMR register to “001b” (Clock synchronous serial I/O mode)
(4) Set the RE bit in the UiC1 register to “1” (reception enabled)
•
(1) Set the SMD2 to SMD0 bits in the UiMR register “000b” (Serial interface disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register “001b” (Clock synchronous serial I/O mode)
(3) “1” is written to RE bit in the UiC1 register (transmission enabled), regardless of the TE bit in the UiCi
Jan 10, 2006
Resetting the UiRB register (i=0 to 2)
Resetting the UiTB register (i=0 to 2)
edge and the receive data taken in at the rising edge of the transfer clock)
data taken in at the falling edge of the transfer clock)
NOTES:
i = 0 to 2
register
1. This applies to the case where the UFORM bit in the UiC0 register = 0
2. When not transferring, the CLKi pin outputs a high signal.
3. When not transferring, the CLKi pin outputs a low signal.
Counter Measure for Communication Error Occurs
CLK Polarity Select Function
Transfer Clock Polarity
(LSB first) and the UiLCH bit in the UiC1 register = 0 (no reverse).
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D0
D0
D0
D0
D1
D1
D1
D1
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
17. Serial Interface
(NOTE 2)
(NOTE 3)