M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 211

IC M16C MCU FLASH 512K 100LQFP

M30626FJPGP#U3C

Manufacturer Part Number
M30626FJPGP#U3C
Description
IC M16C MCU FLASH 512K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets

Specifications of M30626FJPGP#U3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 17.15
17.1.1.3
17.1.1.4
Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 17.15 shows the
Transfer Format.
In continuous receive mode, receive operation becomes enable when the receive buffer register is read. It is not
necessary to write dummy data into the transmit buffer register to enable receive operation in this mode.
However, a dummy read of the receive buffer register is required when starting the operating mode.
When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the TI bit in the UiC1 register is set to “0”
(data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not write
dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the bit 2 and bit 3 in the
UCON register, respectively, and the U2RRM bit is the bit 5 in the U2C1 register.
Jan 10, 2006
(1) When the UFORM bit in the UiC0 register = 0 (LSB first)
(2) When the UFORM bit = 1 (MSB first)
NOTES:
i = 0 to 2
RXDi
RXDi
CLKi
TXDi
CLKi
TXDi
LSB First/MSB First Select Function
Continuous Receive Mode
Transfer Format
1. This applies to the case where the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken in
at the rising edge of the transfer clock) and the UiLCH bit in the UiC1
register = 0 (no reverse).
Page 194 of 390
D0
D0
D7
D7
D1
D6
D1
D6
D2
D5
D2
D5
D3
D4
D3
D4
D4
D3
D4
D3
D5
D2
D5
D2
D6
D6
D1
D1
D7
D7
D0
D0
17. Serial Interface

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