M30626FJPGP#U3C Renesas Electronics America, M30626FJPGP#U3C Datasheet - Page 303

• Manufacturer Part Number: M30626FJPGP#U3C
• Description: IC M16C MCU FLASH 512K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626FJPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
22.3.5
Table 22.4
NOTES:
Read Array
Read Status Register
Clear Status Register
Program
Block Erase
Erase All Unlocked Block
Lock Bit Program
Read Lock Bit Status
22.3.5.1
22.3.5.2
22.3.5.3
1. Blocks 0 to 12 can be erased by the erase all unlocked block command.
Software commands are described below. The command code and data must be read and written in 16-bit units,
to and from even addresses in the user ROM area. When writing command code, the 8 high-order bits (D15 to
D8) are ignored.
The read array command reads the flash memory.
By writing command code “xxFFh” in the first bus cycle, read array mode is entered. Content of a specified
address can be read in 16-bit units after the next bus cycle.
The microcomputer remains in read array mode until another command is written. Therefore, contents from
multiple addresses can be read consecutively.
The read status register command reads the status register (refer to 22.3.7 Status Register for detail).
By writing command code “xx70h” in the first bus cycle, the status register can be read in the second bus cycle.
Read an even address in the user ROM area.
Do not execute this command in EW1 mode.
The clear status register command clears the status register. By writing “xx50h” in the first bus cycle, the
FMR07 to FMR06 bits in the FMR0 register are set to “00b” and the SR5 to SR4 bits in the status register are
set to “00b”.
Block A cannot be erased. The block erase command must be used to erase the block A.
WA:
SRD: Data in the SRD register (D7 to D0)
WD:
BA:
X:
xx:
Jan 10, 2006
Command
Software Commands
Read Array Command (FFh)
Read Status Register Command (70h)
Clear Status Register Command (50h)
Software Commands
address as the address specified in the second bus cycle.)
Address to be written (The address specified in the first bus cycle is the same even
16-bit write data
Highest-order block address (must be an even address)
Any even address in the user ROM space
8 high-order bits of command code (ignored)
Page 286 of 390
Mode
Write
Write
Write
Write
Write
Write
Write
Write
First Bus Cycle
Address
WA
BA
X
X
X
X
X
X
(D0 to D7)
xxFFh
xx20h
xxA7h
xx77h
xx70h
xx50h
xx40h
xx71h
Data
Mode
Read
Write
Write
Write
Write
Write
Second Bus Cycle
22. Flash Memory Version
Address
WA
BA
BA
BA
X
X
(D0 to D7)
xxD0h
xxD0h
xxD0h
xxD0h
Data
SRD
WD