MC68331CEH16 Freescale Semiconductor, MC68331CEH16 Datasheet
MC68331CEH16
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MC68331CEH16 Summary of contents
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... Freescale Semiconductor Technical Summary 32-Bit Modular Microcontroller 1 Introduction The MC68331, a highly-integrated 32-bit microcontroller, combines high-performance data manipula- tion capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that interface through a common intermodule bus (IMB). Standardization facilitates rapid development of devices tailored for specific applications. ...
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... Freescale Semiconductor, Inc. Package Type Temperature 132-Pin PQFP –40 to +85 C –40 to +105 C –40 to +125 C 144-Pin QFP –40 to +85 C –40 to +105 C –40 to +125 C For More Information On This Product, 2 Table 1 Ordering Information Frequency Package Order (MHz) Quantity 16 MHz 2 pc tray 36 pc tray 20 MHz ...
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... Freescale Semiconductor, Inc. Section 1 Introduction 1.1 Features ......................................................................................................................................4 1.2 Block Diagram ............................................................................................................................. 5 1.3 Pin Assignments ..........................................................................................................................6 1.4 Address Map ............................................................................................................................... 8 1.5 Intermodule Bus ..........................................................................................................................8 2 Signal Descriptions 2.1 Pin Characteristics ......................................................................................................................9 2.2 MCU Power Connections .......................................................................................................... 10 2.3 MCU Driver Types ..................................................................................................................... 10 2.4 Signal Characteristics ................................................................................................................10 2.5 Signal Function .......................................................................................................................... 11 3 System Integration Module 3 ...
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... Freescale Semiconductor, Inc. 1.1 Features • Modular Architecture • Central Processing Unit (CPU32) — Upward Object Code Compatible — New Instructions for Controller Applications — 32-Bit Architecture — Virtual Memory Implementation — Loop Mode of Instruction Execution — Table Lookup and Interpolate Instruction — ...
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... Freescale Semiconductor, Inc. 1.2 Block Diagram PWMA PWMA PWMB PWMB PCLK PCLK PAI PAI PGP7/IC4/OC5/OC1 PGP7/IC4/OC5/OC1 PGP6/OC4/OC1 PGP6/OC4/OC1 PGP5/OC3/OC1 PGP5/OC3/OC1 PGP4/OC2/OC1 PGP4/OC2/OC1 PGP3/OC1 PGP3/OC1 PGP2/IC3 PGP2/IC3 PGP1/IC2 PGP1/IC2 PGP0/IC1 PGP0/IC1 RXD PQS7/TXD TXD PQS6/PCS3 PCS3 PQS5/PCS2 PCS2 PQS4/PCS1 PCS1 PQS3/PCS0/SS PCS0/SS ...
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... Freescale Semiconductor, Inc. 1.3 Pin Assignments ADDR1 20 ADDR2 21 ADDR3 22 ADDR4 23 ADDR5 24 ADDR6 25 ADDR7 26 ADDR8 ADDR9 30 ADDR10 31 ADDR11 32 ADDR12 ADDR13 35 ADDR14 36 ADDR15 37 ADDR16 ADDR17 41 ADDR18 42 PQS0/MISO 43 PQS1/MOSI 44 PQS2/SCK 45 PQS3/PCS0/SS 46 PQS4/PCS1 47 PQS5/PCS2 48 PQS6/PCS3 Figure 2 MC68331 132-Pin QFP Pin Assignments For More Information On This Product, ...
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... Freescale Semiconductor, Inc FC0/CS3 4 FC1/CS4 5 FC2/CS5 6 ADDR19/CS6 ADDR20/CS7 7 8 ADDR21/CS8 ADDR22/CS9 9 10 ADDR23/CS10 PCLK 14 PWMB 15 PWMA PAI 23 PGP7/IC4/OC5/OC1 24 PGP6/OC4 PGP5/OC3/OC1 PGP4/OC2/OC1 29 30 PGP3/OC1 31 PGP2/IC3 32 PGP1/IC2 33 PGP0/IC1 Figure 3 MC68331 144-Pin QFP Pin Assignments For More Information On This Product, MC68331TS/D MC68331 Go to: www.freescale.com ...
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... Freescale Semiconductor, Inc. 1.4 Address Map The following figure is a map of the MCU internal addresses. Unimplemented blocks are mapped ex- ternally. $YFF000 $YFF900 $YFF93F $YFFA00 $YFFA7F $YFFA80 $YFFAFF $YFFC00 $YFFDFF $YFFFFF 1.5 Intermodule Bus The intermodule bus (IMB standardized bus developed to facilitate both design and operation of modular microcontrollers ...
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... Freescale Semiconductor, Inc. 2 Signal Descriptions 2.1 Pin Characteristics The following table shows MCU pins and their characteristics. All inputs detect CMOS logic levels. All inputs can be put in a high-impedance state, but the method of doing this differs depending upon pin function. Refer to Table 4 , for a description of output drivers. An entry in the discrete I/O column of Ta- ble 2 indicates that a pin has an alternate I/O function ...
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... Freescale Semiconductor, Inc. Table 2 MCU Pin Characteristics (Continued) Pin Mnemonic RXD SCK SIZ[1:0] TSC TXD 2 XFC 2 XTAL NOTES: 1. DATA[15:0] are synchronized during reset only. MODCLK is synchronized only when used as an input port pin. 2. EXTAL, XFC, and XTAL are clock reference connections. ...
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... Freescale Semiconductor, Inc. Table 5 MCU Signal Characteristics (Continued) Signal Name DSACK[1:0] DSCLK DSI DSO EXTAL FC[2:0] FREEZE HALT IC[4:1] IFETCH IPIPE IRQ[7:1] MISO MODCLK MOSI OC[5:1] PAI PC[6:0] PCS[3:0] PE[7:0] PF[7:0] PQS[7:0] PCLK PWMA, PWMB QUOT RESET RMC R/W RXD SCK ...
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... Freescale Semiconductor, Inc. Table 6 MCU Signal Function (Continued) Signal Name Mnemonic Boot Chip Select CSBOOT Data Bus DATA[15:0] Data Strobe Data and Size Acknowledge DSACK[1:0] Development Serial In, Out, DSI, DSO, Clock Crystal Oscillator EXTAL, XTAL Connections for clock synthesizer circuit reference; ...
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... Freescale Semiconductor, Inc. For More Information On This Product, MC68331TS/D Go to: www.freescale.com 13 ...
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... Freescale Semiconductor, Inc. 3 System Integration Module The system integration module (SIM) consists of five functional blocks that control system start-up, ini- tialization, configuration, and external bus. SYSTEM CONFIGURATION CLOCK SYNTHESIZER SYSTEM PROTECTION CHIP SELECTS EXTERNAL BUS INTERFACE FACTORY TEST 3.1 Overview The system configuration and protection block controls MCU configuration and operating mode. The block also provides bus and software watchdog monitors ...
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... Freescale Semiconductor, Inc. Access Address 15 S $YFFA00 S $YFFA02 S $YFFA04 S $YFFA06 S $YFFA08 S $YFFA0A S $YFFA0C S $YFFA0E S/U $YFFA10 S/U $YFFA12 S/U $YFFA14 S $YFFA16 S/U $YFFA18 S/U $YFFA1A S/U $YFFA1C S $YFFA1E S $YFFA20 S $YFFA22 S $YFFA24 S $YFFA26 S $YFFA28 S $YFFA2A S $YFFA2C S $YFFA2E S $YFFA30 S $YFFA32 S $YFFA34 S $YFFA36 S $YFFA38 ...
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... Freescale Semiconductor, Inc. Table 7 SIM Address Map (Continued) Access Address 15 S $YFFA5E S $YFFA60 S $YFFA62 S $YFFA64 S $YFFA66 S $YFFA68 S $YFFA6A S $YFFA6C S $YFFA6E S $YFFA70 S $YFFA72 S $YFFA74 S $YFFA76 $YFFA78 $YFFA7A $YFFA7C $YFFA7E Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR. 3.2 System Configuration and Protection This functional block provides configuration control for the entire MCU ...
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... Freescale Semiconductor, Inc. SPURIOUS INTERRUPT MONITOR CLOCK PRESCALER 9 2 Figure 6 System Configuration and Protection Block 3.2.1 System Configuration The SIM controls MCU configuration during normal operation and during internal testing. SIMCR —SIM Configuration Register EXOFF FRZSW FRZBM 0 SLVEN RESET DATA11 The SIM configuration register controls system configuration. It can be read or written at any time, ex- cept for the module mapping (MM) bit, which can be written only once. EXOFF — ...
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... Freescale Semiconductor, Inc. SLVEN —Factory Test Mode Enabled This bit is a read-only status bit that reflects the state of DATA11 during reset IMB is not available to an external master external bus master has direct access to the IMB. SHEN[1:0] —Show Cycle Enable This field determines what the EBI does with the external bus during internal transfer operations. A show cycle allows internal transfers to be externally monitored ...
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... Freescale Semiconductor, Inc. SWP —Software Watchdog Prescale This bit controls the value of the software watchdog prescaler Software watchdog clock not prescaled 1 = Software watchdog clock prescaled by 512 SWT[1:0] —Software Watchdog Timing This field selects the divide ratio used to establish software watchdog time-out period. The following ta- ble gives the ratio for each combination of SWP and SWT bits ...
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... Freescale Semiconductor, Inc. 3.2.5 Spurious Interrupt Monitor The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an interrupt-ac- knowledge cycle. 3.2.6 Software Watchdog The software watchdog is controlled by SWE in the SYPCR. Once enabled, the watchdog requires that a service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watch- dog times out and issues a reset. This register can be written at any time, but returns zeros when read. SWSR — ...
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... Freescale Semiconductor, Inc. PIRQL PIV[7:0] —Periodic Interrupt Vector The bits of this field contain the vector generated in response to an interrupt from the periodic timer. When the SIM responds, the periodic interrupt vector is placed on the bus. PITR —Periodic Interrupt Timer Register RESET The PITR contains the count value for the periodic timer. A zero value turns off the periodic timer. This register can be read or written at any time. PTP — ...
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... Freescale Semiconductor, Inc. 32.768 KHz 330K R3 10M V V SSI SSI EXTAL XTAL CRYSTAL PHASE OSCILLATOR COMPARATOR 1. MUST BE LOW-LEAKAGE CAPACITOR (INSULATION RESISTANCE 30,000 M OR GREATER). 2. RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768-kHz CRYSTAL. SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT. ...
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... Freescale Semiconductor, Inc. 3.3.2 Clock Synthesizer Operation A voltage controlled oscillator (VCO) generates the system clock signal. A portion of the clock signal is fed back to a divider/counter. The divider controls the frequency of one input to a phase comparator. The other phase comparator input is a reference signal, either from the internal oscillator or from an external source ...
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... Freescale Semiconductor, Inc. When the on-chip clock synthesizer is used, system clock frequency is controlled by the bits in the upper byte of SYNCR. Bits in the lower byte show status of or control operation of internal and external clocks. The SYNCR can be read or written only when the CPU is operating at the supervisor privilege level. ...
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... Freescale Semiconductor, Inc. Port width is the maximum number of bits accepted or provided during a bus transfer. External devices must follow the handshake protocol described below. Control signals indicate the beginning of the cycle, the address space, the size of the transfer, and the type of cycle. The selected device controls the length of the cycle ...
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... Freescale Semiconductor, Inc. 3.4.4 Address Strobe timing signal that indicates the validity of an address on the address bus and the validity of many control signals asserted one-half clock after the beginning of a bus cycle. 3.4.5 Data Bus Data bus signals DATA[15:0] make up a bidirectional, non-multiplexed parallel bus that transfers data to or from the MCU ...
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... Freescale Semiconductor, Inc. For example, if the MCU is executing an instruction that reads a long-word operand from a 16-bit port, the MCU latches the 16 bits of valid data and then runs another bus cycle to obtain the other 16 bits. The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the DSACK0 and DSACK1 signals to indicate the port width ...
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... Freescale Semiconductor, Inc. Transfer Case Byte to 8-Bit Port (Even/Odd) Byte to 16-Bit Port (Even) Byte to 16-Bit Port (Odd) Word to 8-Bit Port (Aligned) 3 Word to 8-Bit Port (Misaligned) Word to 16-Bit Port (Aligned) 3 Word to 16-Bit Port (Misaligned Byte to 8-Bit Port (Aligned Byte to 8-Bit Port (Misaligned) ...
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... Freescale Semiconductor, Inc. INTERNAL BASE ADDRESS REGISTER SIGNALS ADDRESS ADDRESS COMPARATOR BUS CONTROL AVEC AVEC GENERATOR DSACK Figure 9 Chip-Select Circuit Block Diagram The following table lists allocation of chip-selects and discrete outputs on the pins of the MCU. Pin CSBOOT BR BG BGACK FC0 FC1 ...
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... Freescale Semiconductor, Inc. 3.5.2 Pin Assignment Registers The pin assignment registers (CSPAR0 and CSPAR1) contain pairs of bits that determine the function of chip-select pins. The pin assignment encodings used in these registers are shown below. Table 12 Pin Assignment Encodings Bit Field CSPAR0 —Chip Select Pin Assignment Register 0 ...
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... Freescale Semiconductor, Inc. At reset, either the alternate function (01) or chip-select function (11) can be encoded. DATA pins are driven to logic level one by a weak internal pull-up during reset. Encoding is for chip-select function un- less a data line is held low during reset. Note that bus loading can overcome the weak pull-up and hold pins low during reset ...
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... Freescale Semiconductor, Inc. Block Size Field 000 001 010 011 100 101 110 111 ADDR[23:11] —Base Address Field This field sets the starting address of a particular address space. The address compare logic uses only the most significant bits to match an address within a block. The value of the base address must be a multiple of block size ...
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... Freescale Semiconductor, Inc. R/W —Read/Write This field causes a chip select to be asserted only for a read, only for a write, or for both read and write. Refer to the following table for options available. STRB —Address Strobe/Data Strobe 0 = Address strobe 1 = Data strobe This bit controls the timing for assertion of a chip select in asynchronous mode. Selecting address strobe causes chip select to be asserted synchronized with address strobe ...
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... Freescale Semiconductor, Inc. SPACE —Address Space Use this option field to select an address space for the chip-select logic. The CPU32 normally operates in supervisor or user space, but interrupt acknowledge cycles must take place in CPU space. Space Field IPL —Interrupt Priority Level If the space field is set for CPU space (00), chip-select logic can be used for interrupt acknowledge. ...
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... Freescale Semiconductor, Inc. 3.6 General-Purpose Input/Output SIM pins can be configured as two general-purpose I/O ports, E and F. The following paragraphs de- scribe registers that control the ports. PORTE0, PORTE1 —Port E Data Register 15 NOT USED RESET: A write to the port E data register is stored in the internal data latch and, if any port E pin is configured as an output, the value stored for that bit is driven on the pin ...
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... Freescale Semiconductor, Inc. PORTF0, PORTF1 — Port F Data Register 15 NOT USED RESET: The write to the port F data register is stored in the internal data latch, and if any port F pin is configured as an output, the value stored for that bit is driven onto the pin. A read of the port F data register returns the value at the pin only if the pin is configured as a discrete input ...
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... Freescale Semiconductor, Inc. 3.7 Resets Reset procedures handle system initialization and recovery from catastrophic failure. The MCU per- forms resets with a combination of hardware and software. The system integration module determines whether a reset is valid, asserts control signals, performs basic system configuration based on hard- ware mode-select inputs, then passes control to the CPU ...
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... Freescale Semiconductor, Inc. Module CPU32 GPT QSM 3.7.3 Reset Timing The RESET input must be asserted for a specified minimum period in order for reset to occur. External RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus monitor time-out period) in order to protect write cycles from being aborted by reset. While RESET is asserted, SIM pins are either in a disabled high-impedance state or are driven to their inactive states ...
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... Freescale Semiconductor, Inc. The SIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running and the internal reset signal is asserted for four clock cycles, these modules reset. V VCO frequency ramp time determine how long these four cycles take. Worst case is approximately 15 milliseconds ...
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... Freescale Semiconductor, Inc. Interrupt requests are sampled on consecutive falling edges of the system clock. Interrupt request input circuitry has hysteresis valid, a request signal must be asserted for at least two consecutive clock periods. Valid requests do not cause immediate exception processing, but are left pending. Pending re- quests are processed at instruction boundaries or when exception processing of higher-priority excep- tions is complete ...
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... Freescale Semiconductor, Inc. 3.8.2 Interrupt Processing Summary A summary of the interrupt processing sequence follows. When the sequence begins, a valid interrupt service request has been detected and is pending. A. The CPU finishes higher priority exception processing or reaches an instruction boundary. B. Processor state is stacked. The contents of the status register and program counter are saved. ...
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... Freescale Semiconductor, Inc. For More Information On This Product to: www.freescale.com MC68331TS/D ...
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... Freescale Semiconductor, Inc. 4 Central Processor Unit Based on the powerful MC68020, the CPU32 processing module provides enhanced system perfor- mance and also uses the extensive software base for the Motorola M68000 family. 4.1 Overview The CPU32 is fully object code compatible with the M68000 Family, which excels at processing calcu- lation-intensive algorithms and supporting high-level languages ...
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... Freescale Semiconductor, Inc Figure 10 User Programming Model Figure 11 Supervisor Programming Model Supplement For More Information On This Product (USP CCR 0 A7' (SSP (CCR VBR 2 0 SFC DFC Go to: www.freescale.com Data Registers Address Registers User Stack Pointer Program Counter Condition Code Register Supervisor Stack Pointer ...
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... Freescale Semiconductor, Inc. 4.3 Status Register The status register contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. The lower byte containing the condition codes is the only portion of the register available at the user privilege level referenced as the con- dition code register (CCR) in user programs ...
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... Freescale Semiconductor, Inc. 4.6 Instruction Set Summary Table 20 Instruction Set Summary Instruction Syntax ABCD Dn, Dn (An), (An) ADD Dn, <ea> <ea>, Dn ADDA <ea>, An ADDI #<data>, <ea> ADDQ # <data>, <ea> ADDX Dn, Dn (An), (An) AND <ea>, Dn Dn, <ea> ANDI # <data>, <ea> ANDI to CCR # <data>, CCR ...
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... Freescale Semiconductor, Inc. Table 20 Instruction Set Summary (Continued) Instruction Syntax CMPM (An) , (An) CMP2 <ea>, Rn DBcc Dn, label DIVS/DIVU <ea>, Dn DIVSL/DIVUL <ea> <ea>, Dq <ea> EOR Dn, <ea> EORI # <data>, <ea> EORI to CCR # <data>, CCR 1 EORI <data>, SR EXG Rn, Rn EXT Dn Dn EXTB Dn ILLEGAL none JMP < ...
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... Freescale Semiconductor, Inc. Table 20 Instruction Set Summary (Continued) Instruction Syntax MOVEP Dn, (d16, An) (d16, An), Dn MOVEQ #<data> MOVES Rn, <ea> <ea>, Rn MULS/MULU <ea>, Dn <ea>, Dl <ea> NBCD <ea> NEG <ea> NEGX <ea> NOP none NOT <ea> OR <ea>, Dn Dn, <ea> ORI #<data>, <ea> ORI to CCR #< ...
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... Freescale Semiconductor, Inc. Table 20 Instruction Set Summary (Continued) Instruction Syntax SUB <ea>, Dn Dn, <ea> SUBA <ea>, An SUBI #<data>, <ea> SUBQ #<data>, <ea> SUBX Dn, Dn (An), (An) SWAP Dn TAS <ea> TBLS/TBLU <ea>, Dn Dym : Dyn, Dn TBLSN/TBLUN <ea>, Dn Dym : Dyn, Dn TRAP #<data> TRAPcc none #<data> ...
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... Freescale Semiconductor, Inc. 4.7 Background Debugging Mode The background debugger on the CPU32 is implemented in CPU microcode. The background debug- ging commands are summarized below. Table 21 Background Debugging Mode Command Mnemonic Read D/A Register RDREG/RAREG WDREG/WAREG The data operand is written to the specified address or data ...
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... Freescale Semiconductor, Inc. 5 Queued Serial Module The QSM contains two serial interfaces, the queued serial peripheral interface (QSPI) and the serial communication interface (SCI). 5.1 Overview The QSPI provides easy peripheral expansion or interprocessor communication through a full-duplex, synchronous, three-line bus: data in, data out, and a serial clock. Four programmable peripheral chip- select pins provide addressability for peripheral devices ...
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... Freescale Semiconductor, Inc. Access Address S $YFFC00 S $YFFC02 S $YFFC04 S/U $YFFC06 S/U $YFFC08 S/U $YFFC0A S/U $YFFC0C S/U $YFFC0E S/U $YFFC10 S/U $YFFC12 S/U $YFFC14 S/U $YFFC16 S/U $YFFC18 S/U $YFFC1A S/U $YFFC1C S/U $YFFC1E S/U $YFFC20– $YFFCFF S/U $YFFD00– ...
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... Freescale Semiconductor, Inc. 5.3 QSM Registers QSM registers are divided into four categories: QSM global registers, QSM pin control registers, QSPI submodule registers, and SCI submodule registers. The QSPI and SCI registers are defined in separate sections below. Writes to unimplemented register bits have no meaning or effect, and reads from unim- plemented bits always return a logic zero value ...
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... Freescale Semiconductor, Inc. QTEST — QSM Test Register QTEST is used during factory testing of the QSM. Accesses to QTEST must be made while the MCU is in test mode. QILR — QSM Interrupt Levels Register ILQSPI RESET QILR determines the priority level of interrupts requested by the QSM and the vector used when an in- terrupt is acknowledged. ILQSPI — ...
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... Freescale Semiconductor, Inc. PORTQS — Port QS Data Register 15 NOT USED PORTQS latches I/O data. Writes drive pins defined as outputs. Reads return data present on the pins. To avoid driving undefined data, first write a byte to PORTQS, then configure DDRQS. PQSPAR — PORT QS Pin Assignment Register DDRQS — ...
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... Freescale Semiconductor, Inc. DDRQS determines whether pins are inputs or outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output. DDRQS affects both QSPI function and I/O function. Table 24 Effect of DDRQS on QSM Pin Function QSM Pin MISO MOSI ...
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... Freescale Semiconductor, Inc. QUEUE CONTROL BLOCK 4 QUEUE POINTER COMPARATOR DONE END QUEUE POINTER CONTROL LOGIC STATUS REGISTER CONTROL REGISTERS DELAY COUNTER PROGRAMMABLE LOGIC ARRAY 5.4.1 QSPI Pins Seven pins are associated with the QSPI. When not needed for a QSPI application, they can be con- figured as general-purpose I/O pins ...
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... Freescale Semiconductor, Inc. Pin Names Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select Slave Select 5.4.2 QSPI Registers The programmer's model for the QSPI submodule consists of the QSM global and pin control registers, four QSPI control registers, one status register, and the 80-byte QSPI RAM. ...
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... Freescale Semiconductor, Inc. MSTR — Master/Slave Mode Select 0 = QSPI is a slave device and only responds to externally generated serial data QSPI is system master and can initiate transmission to external SPI devices. MSTR configures the QSPI for either master or slave mode operation. This bit is cleared on reset and may only be written by the CPU. WOMQ — ...
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... Freescale Semiconductor, Inc. SPBR — Serial Clock Baud Rate The QSPI uses a modulus counter to derive SCK baud rate from the MCU system clock. Baud rate is selected by writing a value from 2 to 255 into the SPBR field. The following equation determines the SCK baud rate: SPBR = System Clock/(2SCK)(Baud Rate Desired) where SPBR equals { ...
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... Freescale Semiconductor, Inc. SPCR2 — QSPI Control Register SPIFIE WREN WRTO 0 RESET SPCR2 contains QSPI configuration parameters. The CPU can read and write this register; the QSM has read access only. Writes to SPCR2 are buffered. A write to SPCR2 that changes a bit value while the QSPI is operating is ineffective on the current serial transfer, but becomes effective on the next se- rial transfer ...
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... Freescale Semiconductor, Inc. HALT — Halt 0 = Halt not enabled 1 = Halt enabled When HALT is asserted, the QSPI stops on a queue boundary defined state from which it can later be restarted. SPSR — QSPI Status Register 15 SPCR3 SPSR contains QSPI status information. Only the QSPI can assert the bits in this register. The CPU reads this register to obtain status information and writes it to clear status flags. SPIF — ...
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... Freescale Semiconductor, Inc. RR0 500 RR1 RR2 RECEIVE RAM RRD RRE RRF 51E WORD Once the CPU has set up the queue of QSPI commands and enabled the QSPI, the QSPI can operate independently of the CPU. The QSPI executes all of the commands in its queue, sets a flag indicating that it is finished, and then either interrupts the CPU or waits for CPU intervention ...
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... Freescale Semiconductor, Inc. Command RAM consists of 16 bytes. Each byte is divided into two fields. The peripheral chip-select field enables peripherals for transfer. The command control field provides transfer options. A maximum of 16 commands can be in the queue. Queue execution by the QSPI proceeds from the address in NEWQP through the address in ENDQP. (Both of these fields are in SPCR2.) CONT — ...
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... Freescale Semiconductor, Inc. 5.5.1 SCI Pins There are two unidirectional pins associated with the SCI. The SCI controls the transmit data (TXD) pin when enabled, whereas the receive data (RXD) pin remains a dedicated input pin to the SCI. TXD is available as a general-purpose I/O pin when the SCI transmitter is disabled. When used for I/O, TXD can be configured either as input or output, as determined by QSM register DDRQS ...
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... Freescale Semiconductor, Inc. Nominal Baud Rate Actual Rate with 16.78-MHz Clock 64* 110 110.0 300 299.9 600 599.9 1200 1199.7 2400 2405.0 4800 4810.0 9600 9532.5 19200 19418.1 38400 37449.1 76800 74898.3 Maximum Rate 524288.0 *A rate of 64 baud is not available with a 20.97-MHz system clock. To achieve this rate, the SYNCR can be pro- grammed to generate a lower system clock rate. SCCR1 — ...
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... Freescale Semiconductor, Inc. PT — Parity Type 0 = Even parity 1 = Odd parity When parity is enabled, PT determines whether parity is even or odd for both the receiver and the trans- mitter. PE — Parity Enable 0 = SCI parity disabled 1 = SCI parity enabled PE determines whether parity is enabled or disabled for both the receiver and the transmitter. If the re- ceived parity bit is not correct, the SCI sets the PF error flag in SCSR ...
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... Freescale Semiconductor, Inc. RWU — Receiver Wakeup 0 = Normal receiver operation (received data recognized Wakeup mode enabled (received data ignored until awakened) Setting RWU enables the wakeup function, which allows the SCI to ignore received data until awakened by either an idle line or address mark (as determined by WAKE). When in wakeup mode, the receiver status flags are not set, and interrupts are inhibited ...
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... Freescale Semiconductor, Inc. RAF — Receiver Active Flag 0 = SCI receiver is idle 1 = SCI receiver is busy RAF indicates whether the SCI receiver is busy set when the receiver detects a possible start bit and is cleared when the chosen type of idle line is detected. RAF can be used to reduce collisions in systems with multiple masters. IDLE — ...
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... Freescale Semiconductor, Inc. 6 General-Purpose Timer Module The 11-channel general-purpose timer (GPT) is used in systems where a moderate level of CPU control is required. The GPT consists of a capture/compare unit, a pulse accumulator, and two pulse-width modulators. A bus interface unit connects the GPT to the intermodule bus. IC1/PGP0 ...
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... Freescale Semiconductor, Inc. Access Address 15 S $YFF900 S $YFF902 S $YFF904 U $YFF906 PGP DATA DIRECTION (DDRGP) U $YFF908 OC1 ACTION MASK (OC1M) U $YFF90A U $YFF90C U $YFF90E U $YFF910 U $YFF912 U $YFF914 U $YFF916 U $YFF918 U $YFF91A U $YFF91C U $YFF91E TIMER CONTROL 1 (TCTL1) U $YFF920 U $YFF922 U $YFF924 FORCE COMPARE (CFORC) U $YFF926 U $YFF928 ...
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... Freescale Semiconductor, Inc. PCLK PRESCALER – DIVIDE BY SYSTEM 4, 8, 16, 32, 64, 128, 256 CLOCK SELECT CPR2 CPR1 CPR0 16-BIT TIMER BUS 16-BIT LATCH CLK TIC1 (HI) TIC1 (LO) 16-BIT LATCH CLK TIC2 (HI) TIC2 (LO) 16-BIT LATCH CLK TIC3 (HI) TIC3 (LO) = 16-BIT COMPARATOR TOC1 (HI) TOC1 (LO) = 16-BIT COMPARATOR ...
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... Freescale Semiconductor, Inc. SYSTEM CLOCK DIVIDER PCLK SYNCHRONIZER AND PIN DIGITAL FILTER Figure 17 Prescaler Block Diagram For More Information On This Product, MC68331TS/D 512 TO PULSE ACCUMULATOR EXT. TO PULSE ACCUMULATOR TO PULSE ACCUMULATOR CPR2 CPR1 CPR0 256 128 64 TO CAPTURE/ COMPARE 32 16 SELECT 8 4 EXT. ...
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... Freescale Semiconductor, Inc. R PWMA LATCH PIN S F1A ZERO DETECTOR BIT SFA BIT [14:0] 16-BIT COUNTER FROM PRESCALER CLOCK Figure 18 PWM Unit Block Diagram 6.3 Pulse-Width Modulator The pulse-width modulation submodule has two output pins. The outputs are periodic waveforms con- trolled by a single frequency whose duty cycles can be independently selected and modified by user software ...
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... Freescale Semiconductor, Inc. 6.4 GPT Registers GPTMCR — GPT Module Configuration Register STOP FRZ1 FRZ0 STOPP INCP RESET The GPTMCR contains parameters for configuring the GPT. STOP — Stop Clocks 0 = Internal clocks not shut down 1 = Internal clocks shut down FRZ1 — Not implemented at this time FRZ0 — ...
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... Freescale Semiconductor, Inc. DDRGP/PORTGP — Port GP Data Direction Register/Port GP Data Register DDGP7 DDGP6 DDGP5 DDGP4 DDGP3 DDGP2 DDGP1 DDGP0 RESET When GPT pins are used as an 8-bit port, DDRGP determines whether pins are input or output and PORTGP holds the 8-bit data. ...
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... Freescale Semiconductor, Inc. PAMOD — Pulse Accumulator Mode 0 = External event counting 1 = Gated time accumulation PEDGE — Pulse Accumulator Edge Control The effects of PEDGE and PAMOD are shown in the following table. PAMOD PCLKS — PCLK Pin State (Read Only) I4/O5 — Input Capture 4/Output Compare 5 ...
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... Freescale Semiconductor, Inc. OM/OL[5:2] — Output Compare Mode Bits and Output Compare Level Bits Each pair of bits specifies an action to be taken when output comparison is successful. OM/OL[5: EDGE[4:1] — Input Capture Edge Control Bits Each pair of bits configures input sensing logic for the corresponding input capture. ...
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... Freescale Semiconductor, Inc. CPR[2:0] — Timer Prescaler/PCLK Select Field This field selects one of seven prescaler taps or PCLK to be TCNT input. TFLG1/TFLG2 — Timer Interrupt Flag Registers 1– I4/O5F OCF RESET These registers show condition flags that correspond to various GPT events. If the corresponding inter- rupt enable bit in TMSK1/TMSK2 is set, an interrupt occurs. I4/O5F — ...
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... Freescale Semiconductor, Inc. FOC[5:1] — Force Output Compare 0 = Has no meaning 1 = Causes pin action programmed for corresponding OC pin, but the OC flag is not set. FOC[5:1] correspond to OC[5:1]. FPWMA — Force PWMA Value 0 = Normal PWMA operation 1 = The value of F1A is driven out on the PWMA pin, regardless of the state of PPROUT. ...
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... Freescale Semiconductor, Inc. F1B — Force Logic Level One on PWMB 0 = Force logic level zero output on PWMB pin 1 = Force logic level one output on PWMB pin PWMA/PWMB — PWM Control Registers A/B These registers are associated with the pulse-width value of the PWM output on the corresponding PWM pin ...
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... Freescale Semiconductor, Inc. 7 Summary of Changes This is a complete revision, with complete reprint. All known errors in the publication have been correct- ed. The following summary lists significant changes. Typographical errors that do not affect content are not annotated. Page 2 Revised ordering information. Page 5 New block diagram drawn. ...
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... Freescale Semiconductor, Inc. For More Information On This Product, MC68331TS/D Go to: www.freescale.com 83 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...