M30833FJGP#U3 Renesas Electronics America, M30833FJGP#U3 Datasheet - Page 350
M30833FJGP#U3
Manufacturer Part Number
M30833FJGP#U3
Description
IC M32C/83 MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30833FJGPU3.pdf
(96 pages)
3.M30833FJGPU3.pdf
(529 pages)
Specifications of M30833FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Family Name
R8C
Maximum Speed
32 MHz
Operating Supply Voltage
5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
87
Interface Type
UART
On-chip Adc
26-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
11
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Chapter 7
7.1 String Instruction, Product-Sum Operation Instruction
1 .
0
9
The string instructions and the product sum operation instruction listed in 7.1.1. Subject Instructions will
be aborted under the conditions listed in 7.1.2 Problem Conditions.
0 .
B
7.1.1 Subject Instructions
7.1.2 Problem Conditions
7.1.3 Operation Check
7.1.4 Countermeasure Program
0
0
String instructions: SCMPU, SIN, SMOVB, SMOVF, SMOVU, SOUT, SSTR
Product sum operation instruction: RMPA
When DMAC is not used:
1) (a) The interrupt A is requested when bits ILVL2 to ILVL0 in the interrupt control registers are set to
When DMAC is used,
2) (a) The interrupt A is requested when bits ILVL2 to ILVL0 are set to other than 000b. However, the
3) (a) Interrupts are generated immediately before or in the middle of executing the subject instruction.
If DMA transfer occurs in conditions 2)-(c) or 3)-(c), the subject instruction is aborted.
The patterns for the above conditions 1) through 3) are illustrated in Figure 7.1.
Use the flow chart in Figure 7.2 to determine whether the countermeasure programs are needed.
When the countermeasure is needed, refer to 7.1.4.
To execute the subject instruction, interrupts need to be disabled. If interrupts cannot be disabled, use
the countermeasure program in Figure 7.3.
3
1
2
(b) After (a), set the IR bit in the interrupt control register for the interrupt A to 0 (no interrupt request)
(b) After (a), set the IR bit for the interrupt A to 0 by program or set the interrupt priority level smaller
(b) After (a), set the IR bit for the interrupt A to 0 by program or set the interrupt priority level smaller
(c) After (b), execute the subject instruction within next three instructions after setting the I flag to 1
(c) After (b), execute the subject instruction, SCMPU, SIN, SMOVB, SMOVF, SMOVU, SOUT,
(c) After (b), execute the subject instructions after the interrupts are completed with the REIT
9
0
0 -
0
6
other than 000b (level 0, interrupt disabled). However, the interrupt request is not acknowledged
0, interrupt disabled) in the interrupt routine. However, the interrupt request is not acknowledged
1
or IPL to smaller priority than the interrupt priority level, which is set when an interrupt request is
because the I flag is set to 0 (interrupt disabled) or the requested interrupt has smaller priority
level than IPL (IPL interrupt priority level < 001b) while the interrupt is requested.
by program or set the interrupt priority level smaller than the last set level.
SSTR, or RMPA, immediately after setting the I flag to 1 or IPL to smaller priority than the
interrupt priority level, which is set when an interrupt request is generated, to enable the
requested interrupt.
than the last set level.
generated, to enable the requested interrupt.
The interrupt A request is generated when bits ILVL2 to ILVL0 are set to other than 000b (level
because I flag is set to 0 or because IPL is equal to or greater than the interrupt priority level
even if I flag is set to 1 (multiple interrupts enabled).
than the last set level.
instruction or FREIT instruction.
0 .
interrupt request is not acknowledged because the I flag is set to 0 or the requested interrupt
has smaller priority level than IPL (IPL interrupt priority level < 001b) while the interrupt is
requested.
0
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3 .
Precautions
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5
7.1
String/Product-Sum Operation Instruction
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