MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 230

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

6.13.1.2 Internal Memory Map Register
MPC555
USER’S MANUAL
IMMR — Internal Memory Mapping Register
MLRC
NOTES:
MSB
16
00
01
10
11
0
0
RESET:
RESET:
1. Operates as MODCK[1] during reset.
2. This holds if MTSC bit is reset to 0. Otherwise IRQ[2]/CR/SGPIOC[2]/MTS will function as MTS.
The internal memory map register (IMMR) is a special register located within the
MPC555 / MPC556 special register space. The IMMR contains identification of a spe-
cific device as well as the base for the internal memory map. Based on the value read
from this register, software can deduce availability and location of any on-chip system
resources.
This register can be read by the mfspr instruction. The ISB field can be written by the
mtspr instruction. The PARTNUM and MASKNUM fields are mask programmed and
cannot be changed.
* The reset value is a reset configuration word value extracted from the indicated bits of the internal data bus. Refer
to
7.5.2 Hard Reset Configuration
RESERVED
17
/
1
0
MPC556
SGPIOC[0]
SGPIOC[0]
IRQ[0]/
IRQ[0]
IRQ[0]
IRQ[0]
Table 6-10 Multi-Level Reservation Control Pin Configuration
18
2
0
Read-Only Fixed Value
PARTNUM
19
3
0
IRQ[1]/RSV/
SGPIOC[1]
SGPIOC[1]
FLEN
ID20*
Freescale Semiconductor, Inc.
SYSTEM CONFIGURATION AND PROTECTION
20
4
IRQ[1]
IRQ[1]
For More Information On This Product,
RSV
RESERVED
21
5
0
Word.
Go to: www.freescale.com
Rev. 15 October 2000
22
6
0
SGPIOC[2]
SGPIOC[2]
SGPIOC[2]/
IRQ[2]/CR/
IRQ[2]
MTS
CR
CLES
ID23*
23
7
2
Pin Function
2
2
2
24
8
0
SGPIOC[3]
IRQ[3]/KR/
KR/RETRY
SGPIOC[3]
KR/RETRY
RESERVED
RETRY /
25
IRQ[3]
9
0
10
26
0
Read-Only Fixed Value
MASKNUM
11
27
IRQ[4]/AT[2]/
0
SGPIOC[4]
SGPIOC[4]
IRQ[4]
AT[2]
AT[2]
12
28
ID[28:30]*
ISB
13
29
IRQ[5]/SGPI-
MODCK[1]
SGPIOC[5]/
SGPIOC[5]/
MODCK[1]
MODCK[1]
MODCK[1]
MODCK[1]
MOTOROLA
SPR 638
IRQ[5] /
IRQ[5] /
14
30
OC[5]/
LSB
15
31
6-22
0
0
1