MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 326

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

9.5.6 Arbitration Phase
MPC555
USER’S MANUAL
Half-word
Transfer
Word
Size
Byte
NOTE: “—” denotes a byte not required during that read cycle.
Table 9-3
MPC556 initiates an access.
NOTE: “—” denotes a byte not driven during that write cycle.
The external bus design provides for a single bus master at any one time, either the
MPC555 / MPC556 or an external device. One or more of the external devices on the
bus can have the capability of becoming bus master for the external bus. Bus arbitra-
tion may be handled either by an external central bus arbiter or by the internal on-chip
arbiter. In the latter case, the system is optimized for one external bus master besides
the MPC555 / MPC556. The arbitration configuration (external or internal) is set at sys-
tem reset.
Each bus master must have bus request (BR), bus grant (BG), and bus busy (BB) sig-
nals. The device that needs the bus asserts BR. The device then waits for the arbiter
to assert BG. In addition, the new master must look at BB to ensure that no other mas-
ter is driving the bus before it can assert BB to assume ownership of the bus. Any time
the arbiter has taken the bus grant away from the master and the master wants to ex-
Half-word
/
Transfer
MPC556
Word
Size
Byte
TSIZE
[0:1]
01
01
01
01
10
10
00
lists the patterns of the data transfer for write cycles when the MPC555 /
Table 9-2 Data Bus Requirements For Read Cycles
TSIZE[0:1]
Address
[30:31]
Table 9-3 Data Bus Contents for Write Cycles
ADDR
01
01
01
01
10
10
00
00
01
10
11
00
10
00
Freescale Semiconductor, Inc.
For More Information On This Product,
DATA
Address
[0:7]
OP0
OP0
OP0
[30:31]
ADDR
—
—
—
—
EXTERNAL BUS INTERFACE
00
01
10
11
00
10
00
Go to: www.freescale.com
Rev. 15 October 2000
DATA
[8:15]
OP1
OP1
OP1
—
—
—
—
32-bit Port Size
DATA
[0:7]
OP0
OP1
OP2
OP3
OP0
OP2
OP0
[16:23]
DATA
OP2
OP2
OP2
—
—
—
—
External Data Bus Pattern
DATA
[8:15]
OP1
OP3
OP1
OP3
OP1
—
—
[24:31]
DATA
OP3
OP3
OP3
—
—
—
—
[16:23]
DATA
OP2
OP2
OP2
—
—
—
—
DATA
[0:7]
16-bit Port Size
OP0
OP2
OP0
OP2
OP0
—
—
[24:31]
DATA
DATA
[8:15]
OP3
OP3
OP3
OP1
OP3
OP1
OP3
OP1
—
—
—
—
—
—
MOTOROLA
DATA
8-bit
[0:7]
Port
Size
OP0
OP1
OP2
OP3
OP0
OP2
OP0
9-30