MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 405

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

12.4 Interrupt Operation
MPC555
USER’S MANUAL
Table 12-2
form each type of bus cycle. It is assumed in this table that the IMB3 is available to the
UIMB at all times (fastest possible case).
The interrupts from the modules on the IMB3 are propagated to the interrupt controller
in the USIU through the UIMB interface. The UIMB interrupt synchronizer latches the
Interrupts from the IMB3 and drives them onto the U-bus, where they are latched by
the USIU interrupt controller.
CLKOUT
IMB Clock
CLKOUT
IMB Clock
/
MPC556
Bus Cycle (from U-bus Transfer Start
The UIMB interface dynamically interprets the port size of the ad-
dressed module during each bus cycle, allowing bus transfers to and
from 16-bit and 32-bit IMB modules. During a bus transaction, the
slave module on the IMB signals its port size (16- or 32-bit) via an in-
ternal port size signal.
to U-bus Transfer Acknowledge)
shows the number of system clock cycles that the UIMB requires to per-
Table 12-2 Bus Cycles and System Clock Cycles
Dynamically-sized write
Dynamically-sized read
Figure 12-3 IMB Clock – Half-Speed IMB Bus
Figure 12-2 IMB Clock – Full-Speed IMB Bus
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
Normal write
Freescale Semiconductor, Inc.
Normal read
For More Information On This Product,
U-BUS TO IMB3 BUS INTERFACE (UIMB)
B4
B4
Go to: www.freescale.com
B1
Rev. 15 October 2000
B2
B1
NOTE
B3
Number of System Clock Cycles
Full Speed
4
4
6
6
B4
B2
B1
6
6
10
10
Half Speed
B2
B3
B3
MOTOROLA
12-3