MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 429

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

13.10.2 Queue Boundary Conditions
MPC555
USER’S MANUAL
When the QADC64 encounters a CCW with the pause bit set, the queue enters the
paused state after completing the conversion specified in the CCW with the pause bit.
The pause flag is set and a pause software interrupt may optionally be issued. The sta-
tus of the queue is shown to be paused, indicating completion of a sub-queue. The
QADC64 then waits for another trigger event to again begin execution of the next sub-
queue.
The following are queue operation boundary conditions:
Boundary conditions also exist for combinations of pause and end-of-queue. One case
is when a pause bit is in one CCW and an end-of-queue condition is in the next CCW.
The conversion specified by the CCW with the pause bit set completes normally. The
pause flag is set. However, since the end-of-queue condition is recognized, the com-
pletion flag is also set and the queue status becomes idle, not paused. Examples of
this situation include:
• The first CCW in a queue contains channel 63, the end-of-queue (EOQ) code.
• BQ2 (beginning of queue 2) is set at the end of the CCW table (63) and a trigger
• BQ2 is set to CCW0 and a trigger event occurs on queue 1. After reading CCW0,
• BQ2 (beginning of queue 2) is set beyond the end of the CCW table (64 - 127)
• The pause bit is set in CCW5 and the channel 63 (EOQ) code is in CCW6
• The pause bit is set in CCW63
• During queue 1 operation, the pause bit is set in CCW14 and BQ2 points to
/
The queue becomes active and the first CCW is read. The end-of-queue is rec-
ognized, the completion flag is set, and the queue becomes idle. A conversion is
not performed.
event occurs on queue 2.
BQ2. The end-of-queue condition is recognized, a conversion is performed, the
completion flag is set, and the queue becomes idle.
the end-of-queue condition is recognized, the completion flag is set, and the
queue becomes idle. A conversion is not performed.
and a trigger event occurs on queue 2. Refer to 7.6.3 Control Register two for in-
formation on BQ2. The end-of-queue condition is recognized immediately, the
completion flag is set, and the queue becomes idle. A conversion is not per-
formed.
CCW15
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Multiple end-of-queue conditions may be recognized simultaneously,
although there is no change in the QADC64 behavior. For example,
if BQ2 is set to CCW0, CCW0 contains the EOQ code, and a trigger
event occurs on queue 1, the QADC64 reads CCW0 and detects
both end-of-queue conditions. The completion flag is set for queue 1
only and it becomes idle.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 15 October 2000
13.12.8 QADC64 Control Register 2 (QACR2)
NOTE
MOTOROLA
13-17
on