MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 442

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

13.11.1 Interrupt Sources
MPC555
USER’S MANUAL
The QADC64 has four interrupt service sources, each of which is separately enabled.
Each time the result is written for the last CCW in a queue, the completion flag for the
corresponding queue is set, and when enabled, an interrupt request is generated. In
the same way, each time the result is written for a CCW with the pause bit set, the
queue pause flag is set, and when enabled, an interrupt request is generated.
Table 13-5
queue 1 and queue 2 activity.
Both polled and interrupt-driven QADC64 operations require that status flags must be
cleared after an event occurs. Flags are cleared by first reading QASR with the appro-
priate flag bits set to one, then writing zeros to the flags that are to be cleared. A flag
can be cleared only if the flag was a logic one at the time the register was read by the
CPU. If a new event occurs between the time that the register is read and the time that
it is written, the associated flag is not cleared.
Queue 1
Queue 2
Queue
/
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
PIE1
CIE1
PIE2
CIE2
CF1
CF2
PF1
PF2
Table 13-5 QADC64 Status Flags and Interrupt Sources
displays the status flag and interrupt enable bits which correspond to
Result written for the last CCW in queue 1
Result written for a CCW with pause bit set in
queue 1
Result written for the last CCW in queue 2
Result written for a CCW with pause bit set in
queue 2
Figure 13-10 QADC64 Interrupt Flow Diagram
CONVERSION COMPLETE INTERRUPT
CONVERSION COMPLETE INTERRUPT
Freescale Semiconductor, Inc.
CONVERSION COMPLETE FLAG
CONVERSION COMPLETE FLAG
CONVERSION PAUSE ENABLE
CONVERSION PAUSE ENABLE
CONVERSION PAUSE FLAG
CONVERSION PAUSE FLAG
For More Information On This Product,
Queue Activity
Go to: www.freescale.com
Rev. 15 October 2000
ENABLE
ENABLE
QUEUE 1
QUEUE 2
(IRL1)
(IRL2)
Status Flag
CF1
CF2
PF1
PF2
GENERATOR
INTERRUPT
INTERRUPT
CONTROL
Interrupt Enable Bit
CIE1
PIE1
CIE2
PIE2
MOTOROLA
IRQ[7:0]
13-30