MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 464

• Manufacturer Part Number: MPC555LFMZP40
• Description: IC MCU 32BIT 40MHZ 272-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC555LFMZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 101
• Program Memory Size: 448KB (448K x 8)
• Program Memory Type: FLASH
• Ram Size: 26K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 272-PBGA
• Controller Family/series: POWER 5xx
• Ram Memory Size: 26KB
• Cpu Speed: 63MIPS
• Embedded Interface Type: QSPI, SCI, TouCAN
• Operating Temperature Range: -40°C To +125°C
• No. Of Pins: 272
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 26 KB
• Interface Type: CAN, QSPI, SCI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 101
• Operating Supply Voltage: 3.3 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC555CMEE
• Minimum Operating Temperature: - 85 C
• On-chip Adc: 10 bit, 32 Channel
• Cpu Family: MPC55xx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 40MHz
• Total Internal Ram Size: 32KB
• # I/os (max): 101
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 272
• Package Type: BGA
• For Use With: MPC555CMEE - KIT EVAL FOR MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

14.3 Signal Descriptions
14.4 Memory Map
MPC555
USER’S MANUAL
The QSMCM has 12 external pins, as shown in
in use for their submodule function, can be used as general-purpose I/O port pins. The
RXDx and TXDx pins can alternately serve as general-purpose input-only and output-
only signals, respectively. ECK is a dedicated clock pin.
For detailed descriptions of QSMCM signals, refer to
isters,
The QSMCM memory map, shown in
QSPI and dual SCI control and status registers, and the QSPI RAM. The QSMCM
memory map can be divided into supervisor-only data space and assignable data
space. The address offsets shown are from the base address of the QSMCM module.
Refer to
internal memory map.
IMB3*
/
MPC556
14.7.3 QSPI
1.3 MPC555 / MPC556 Address Map
*Note: SBIU Bus and interface to IMB3 are each 16 bits wide.
Freescale Semiconductor, Inc.
Pins, and
QUEUED SERIAL MULTI-CHANNEL MODULE
Figure 14-1 QSMCM Block Diagram
For More Information On This Product,
Receive and Transmit Queue
QSPI QUEUE RAM
Go to: www.freescale.com
14.8.6 SCI
Rev. 15 October 2000
QSPI
SBIU
DSCI
SCI1
SCI2
Table
Pins.
14-1, includes the global registers, the
for a diagram of the MPC555 / MPC556
Figure
14.6 QSMCM Pin Control Reg-
14-1. Seven of the pins, if not
2
7
2
SCK/QGPIO6
PCS1/QGPIO1
PCS2/QGPIO2
PCS3/QGPIO3
RXD1/QGPI1
TXD2/QGPO2
RXD2/QGPI2
MISO/QGPIO4
MOSI/QGPIO5
PCS[0]/SS/QGPIO0
TXD1/QGPO1
MOTOROLA
ECK
14-2