MPC555LFMZP40 Freescale Semiconductor, MPC555LFMZP40 Datasheet - Page 560

IC MCU 32BIT 40MHZ 272-BGA

MPC555LFMZP40

Manufacturer Part Number
MPC555LFMZP40
Description
IC MCU 32BIT 40MHZ 272-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC555LFMZP40

Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
101
Program Memory Size
448KB (448K x 8)
Program Memory Type
FLASH
Ram Size
26K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
272-PBGA
Controller Family/series
POWER 5xx
Ram Memory Size
26KB
Cpu Speed
63MIPS
Embedded Interface Type
QSPI, SCI, TouCAN
Operating Temperature Range
-40°C To +125°C
No. Of Pins
272
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
26 KB
Interface Type
CAN, QSPI, SCI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
101
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
MPC555CMEE
Minimum Operating Temperature
- 85 C
On-chip Adc
10 bit, 32 Channel
Cpu Family
MPC55xx
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
40MHz
Total Internal Ram Size
32KB
# I/os (max)
101
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
272
Package Type
BGA
For Use With
MPC555CMEE - KIT EVAL FOR MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

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Part Number:
MPC555LFMZP40
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MPC555
USER’S MANUAL
Bit(s)
12:15
MDASM Control Register Bits
9:10
7:8
11
6
/
FORCB
MPC556
Name
MOD
BSL
MOD
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 15-17 MDASMSCR Bit Descriptions (Continued)
Force B. In the OCB, OCAB and OPWM modes, the FORCB bit allows the software to force the
output flip-flop to behave as if a successful comparison had occurred on channel B (except that
the FLAG line is not activated). Writing a one to FORCB resets the output flip-flop; writing a zero
to it has no effect.
In the DIS, IPWM, IPM and IC modes, the FORCB bit is not used and writing to it has no effect.
FORCB is cleared by reset and is always read as zero. Writing a one to both FORCA and
FORCB simultaneously resets the output flip-flop.
Reserved
Bus select.These bits are used to select which of the four possible 16-bit counter bus passing
nearby is used by the MDASM. Refer to
the 16-bit counter buses in the MIOS1.
NOTE: In the MPC555 / MPC556, only 0b00 (CB6) and 0b01 (CB22) are implemented.
0
Mode select. These four mode select bits select the mode of operation of the MDASM. To avoid
spurious interrupts, it is recommended that MDASM interrupts are disabled before changing the
operating mode. It is also imperative to go through the disable mode before changing the oper-
ating mode. See
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 15-18 MDASM Mode Selects
Resolution
Bits of
Table 15-18
16
16
16
16
16
16
15
14
13
12
11
9
7
Go to: www.freescale.com
Rev. 15 October 2000
Bus Bits
Counter
Ignored
for details.
0-2
0-3
0-4
0-6
0-8
0,1
0
Table 15-36
Description
DIS – Disabled
IPWM – Input pulse width measurement
IPM – Input period measurement
IC – Input capture
OCB – Output compare, flag on B compare
OCAB – Output compare, flag on A and B compare
Reserved
Reserved
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
OPWM – Output pulse width modulation
to see how the MDASM is connected to
MDASM Mode of Operation
MOTOROLA
15-24

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