AT89C51CC03C-SLRIM Atmel, AT89C51CC03C-SLRIM Datasheet - Page 110
AT89C51CC03C-SLRIM
Manufacturer Part Number
AT89C51CC03C-SLRIM
Description
IC 8051 MCU FLASH 64K 44PLCC
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
2.AT89C51CC03C-S3RIM.pdf
(32 pages)
3.AT89C51CC03C-S3RIM.pdf
(27 pages)
4.AT89C51CC03C-S3RIM.pdf
(184 pages)
Specifications of AT89C51CC03C-SLRIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT89C51CC03CSLRTR
Available stocks
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Part Number
Manufacturer
Quantity
Price
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110
AT89C51CC03
Table 61. CANBT2 Register
CANBT2 (S:B5h)
CAN Bit Timing Registers 2
Note:
No default value after reset.
Number
Bit
6-5
3-1
7
7
4
0
-
The CAN controller bit timing registers must be accessed only if the CAN controller is dis-
abled with the ENA bit of the CANGCON register set to 0.
See Figure 48.
Bit Mnemonic Description
SJW 1
SJW1:0
PRS2:0
6
-
-
-
SJW 0
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Re-synchronization Jump Width
To compensate for phase shifts between clock oscillators of different bus
controllers, the controller must re-synchronize on any relevant signal edge of
the current transmission.
The synchronization jump width defines the maximum number of clock cycles.
A bit period may be shortened or lengthened by a re-synchronization.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Programming Time Segment
This part of the bit time is used to compensate for the physical delay times
within the network. It is twice the sum of the signal propagation time on the
bus line, the input comparator delay and the output driver delay.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
4
-
Tsjw = Tscl x (SJW [1..0] +1)
Tprs = Tscl x (PRS[2..0] + 1)
PRS 2
3
PRS 1
2
4182E–CAN–05/04
PRS 0
1
0
-
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